390f9b8d82
HW Rx descriptor represents many contiguous packet buffers which follow each other. Number of buffers, stride and maximum DMA length are setup-time configurable per Rx queue based on provided mempool. The mempool must support contiguous block allocation and get info API to retrieve number of objects in the block. Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com> Reviewed-by: Ivan Malov <ivan.malov@oktetlabs.ru>
120 lines
3.0 KiB
C
120 lines
3.0 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2017-2018 Solarflare Communications Inc.
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* All rights reserved.
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*
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* This software was jointly developed between OKTET Labs (under contract
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* for Solarflare) and Solarflare Communications, Inc.
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*/
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#ifndef _SFC_EF10_H
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#define _SFC_EF10_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Number of events in one cache line */
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#define SFC_EF10_EV_PER_CACHE_LINE \
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(RTE_CACHE_LINE_SIZE / sizeof(efx_qword_t))
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#define SFC_EF10_EV_QCLEAR_MASK (~(SFC_EF10_EV_PER_CACHE_LINE - 1))
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#if defined(SFC_EF10_EV_QCLEAR_USE_EFX)
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static inline void
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sfc_ef10_ev_qclear_cache_line(void *ptr)
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{
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efx_qword_t *entry = ptr;
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unsigned int i;
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for (i = 0; i < SFC_EF10_EV_PER_CACHE_LINE; ++i)
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EFX_SET_QWORD(entry[i]);
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}
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#else
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/*
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* It is possible to do it using AVX2 and AVX512F, but it shows less
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* performance.
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*/
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static inline void
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sfc_ef10_ev_qclear_cache_line(void *ptr)
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{
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const __m128i val = _mm_set1_epi64x(UINT64_MAX);
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__m128i *addr = ptr;
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unsigned int i;
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RTE_BUILD_BUG_ON(sizeof(val) > RTE_CACHE_LINE_SIZE);
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RTE_BUILD_BUG_ON(RTE_CACHE_LINE_SIZE % sizeof(val) != 0);
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for (i = 0; i < RTE_CACHE_LINE_SIZE / sizeof(val); ++i)
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_mm_store_si128(&addr[i], val);
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}
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#endif
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static inline void
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sfc_ef10_ev_qclear(efx_qword_t *hw_ring, unsigned int ptr_mask,
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unsigned int old_read_ptr, unsigned int read_ptr)
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{
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const unsigned int clear_ptr = read_ptr & SFC_EF10_EV_QCLEAR_MASK;
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unsigned int old_clear_ptr = old_read_ptr & SFC_EF10_EV_QCLEAR_MASK;
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while (old_clear_ptr != clear_ptr) {
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sfc_ef10_ev_qclear_cache_line(
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&hw_ring[old_clear_ptr & ptr_mask]);
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old_clear_ptr += SFC_EF10_EV_PER_CACHE_LINE;
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}
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/*
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* No barriers here.
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* Functions which push doorbell should care about correct
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* ordering: store instructions which fill in EvQ ring should be
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* retired from CPU and DMA sync before doorbell which will allow
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* to use these event entries.
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*/
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}
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static inline bool
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sfc_ef10_ev_present(const efx_qword_t ev)
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{
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return ~EFX_QWORD_FIELD(ev, EFX_DWORD_0) |
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~EFX_QWORD_FIELD(ev, EFX_DWORD_1);
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}
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/**
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* Alignment requirement for value written to RX WPTR:
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* the WPTR must be aligned to an 8 descriptor boundary.
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*/
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#define SFC_EF10_RX_WPTR_ALIGN 8u
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static inline void
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sfc_ef10_rx_qpush(volatile void *doorbell, unsigned int added,
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unsigned int ptr_mask)
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{
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efx_dword_t dword;
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/* Hardware has alignment restriction for WPTR */
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RTE_BUILD_BUG_ON(SFC_RX_REFILL_BULK % SFC_EF10_RX_WPTR_ALIGN != 0);
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SFC_ASSERT(RTE_ALIGN(added, SFC_EF10_RX_WPTR_ALIGN) == added);
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EFX_POPULATE_DWORD_1(dword, ERF_DZ_RX_DESC_WPTR, added & ptr_mask);
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/* DMA sync to device is not required */
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/*
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* rte_write32() has rte_io_wmb() which guarantees that the STORE
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* operations (i.e. Rx and event descriptor updates) that precede
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* the rte_io_wmb() call are visible to NIC before the STORE
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* operations that follow it (i.e. doorbell write).
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*/
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rte_write32(dword.ed_u32[0], doorbell);
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}
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const uint32_t * sfc_ef10_supported_ptypes_get(uint32_t tunnel_encaps);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SFC_EF10_H */
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