c9bb590d42
Add device stats get from reading hardware registers. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
196 lines
5.9 KiB
C
196 lines
5.9 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2015-2020
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*/
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#ifndef _TXGBE_ETHDEV_H_
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#define _TXGBE_ETHDEV_H_
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#include "base/txgbe.h"
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#include "txgbe_ptypes.h"
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/* need update link, bit flag */
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#define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
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#define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
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#define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
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#define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
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#define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
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/*
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* Defines that were not part of txgbe_type.h as they are not used by the
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* FreeBSD driver.
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*/
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#define TXGBE_VLAN_TAG_SIZE 4
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#define TXGBE_HKEY_MAX_INDEX 10
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/*Default value of Max Rx Queue*/
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#define TXGBE_MAX_RX_QUEUE_NUM 128
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#define TXGBE_VMDQ_DCB_NB_QUEUES TXGBE_MAX_RX_QUEUE_NUM
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#define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
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#define TXGBE_RSS_OFFLOAD_ALL ( \
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ETH_RSS_IPV4 | \
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ETH_RSS_NONFRAG_IPV4_TCP | \
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ETH_RSS_NONFRAG_IPV4_UDP | \
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ETH_RSS_IPV6 | \
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ETH_RSS_NONFRAG_IPV6_TCP | \
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ETH_RSS_NONFRAG_IPV6_UDP | \
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ETH_RSS_IPV6_EX | \
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ETH_RSS_IPV6_TCP_EX | \
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ETH_RSS_IPV6_UDP_EX)
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#define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
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#define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
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/* structure for interrupt relative data */
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struct txgbe_interrupt {
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uint32_t flags;
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uint32_t mask_misc;
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/* to save original mask during delayed handler */
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uint32_t mask_misc_orig;
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uint32_t mask[2];
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};
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#define TXGBE_NB_STAT_MAPPING 32
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#define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
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#define NB_QMAP_FIELDS_PER_QSM_REG 4
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#define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
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struct txgbe_stat_mappings {
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uint32_t tqsm[TXGBE_NB_STAT_MAPPING];
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uint32_t rqsm[TXGBE_NB_STAT_MAPPING];
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};
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struct txgbe_uta_info {
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uint8_t uc_filter_type;
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uint16_t uta_in_use;
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uint32_t uta_shadow[TXGBE_MAX_UTA];
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};
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/*
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* Structure to store private data for each driver instance (for each port).
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*/
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struct txgbe_adapter {
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struct txgbe_hw hw;
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struct txgbe_hw_stats stats;
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struct txgbe_interrupt intr;
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struct txgbe_stat_mappings stat_mappings;
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struct txgbe_uta_info uta_info;
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bool rx_bulk_alloc_allowed;
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};
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#define TXGBE_DEV_ADAPTER(dev) \
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((struct txgbe_adapter *)(dev)->data->dev_private)
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#define TXGBE_DEV_HW(dev) \
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(&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)
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#define TXGBE_DEV_STATS(dev) \
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(&((struct txgbe_adapter *)(dev)->data->dev_private)->stats)
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#define TXGBE_DEV_INTR(dev) \
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(&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)
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#define TXGBE_DEV_STAT_MAPPINGS(dev) \
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(&((struct txgbe_adapter *)(dev)->data->dev_private)->stat_mappings)
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#define TXGBE_DEV_UTA_INFO(dev) \
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(&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info)
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/*
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* RX/TX function prototypes
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*/
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void txgbe_dev_clear_queues(struct rte_eth_dev *dev);
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void txgbe_dev_free_queues(struct rte_eth_dev *dev);
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void txgbe_dev_rx_queue_release(void *rxq);
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void txgbe_dev_tx_queue_release(void *txq);
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int txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
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uint16_t nb_rx_desc, unsigned int socket_id,
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const struct rte_eth_rxconf *rx_conf,
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struct rte_mempool *mb_pool);
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int txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
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uint16_t nb_tx_desc, unsigned int socket_id,
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const struct rte_eth_txconf *tx_conf);
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int txgbe_dev_rx_init(struct rte_eth_dev *dev);
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void txgbe_dev_tx_init(struct rte_eth_dev *dev);
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int txgbe_dev_rxtx_start(struct rte_eth_dev *dev);
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void txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
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void txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
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void txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
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void txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
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int txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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int txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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int txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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int txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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void txgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
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struct rte_eth_rxq_info *qinfo);
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void txgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
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struct rte_eth_txq_info *qinfo);
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uint16_t txgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t txgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t txgbe_recv_pkts_lro_single_alloc(void *rx_queue,
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struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
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uint16_t txgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
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struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
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uint16_t txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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uint16_t txgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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uint16_t txgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
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uint8_t queue, uint8_t msix_vector);
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int
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txgbe_dev_link_update_share(struct rte_eth_dev *dev,
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int wait_to_complete);
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#define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
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#define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
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#define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
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/*
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* Default values for RX/TX configuration
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*/
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#define TXGBE_DEFAULT_RX_FREE_THRESH 32
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#define TXGBE_DEFAULT_RX_PTHRESH 8
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#define TXGBE_DEFAULT_RX_HTHRESH 8
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#define TXGBE_DEFAULT_RX_WTHRESH 0
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#define TXGBE_DEFAULT_TX_FREE_THRESH 32
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#define TXGBE_DEFAULT_TX_PTHRESH 32
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#define TXGBE_DEFAULT_TX_HTHRESH 0
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#define TXGBE_DEFAULT_TX_WTHRESH 0
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const uint32_t *txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
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int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
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struct rte_ether_addr *mc_addr_set,
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uint32_t nb_mc_addr);
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void txgbe_dev_setup_link_alarm_handler(void *param);
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void txgbe_read_stats_registers(struct txgbe_hw *hw,
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struct txgbe_hw_stats *hw_stats);
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#endif /* _TXGBE_ETHDEV_H_ */
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