47854c1803
When using RTE_PKTMBUF_HEADROOM as 0, dpaa driver throws compilation error
error "Annotation requirement is more than RTE_PKTMBUF_HEADROOM"
This patch change it into run-time check.
Bugzilla ID: 335
Fixes: ff9e112d78 ("net/dpaa: add NXP DPAA PMD driver skeleton")
Cc: stable@dpdk.org
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
189 lines
5.3 KiB
C
189 lines
5.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved.
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* Copyright 2017 NXP
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*
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*/
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#ifndef __DPAA_ETHDEV_H__
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#define __DPAA_ETHDEV_H__
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/* System headers */
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#include <stdbool.h>
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#include <rte_ethdev_driver.h>
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#include <rte_event_eth_rx_adapter.h>
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#include <fsl_usd.h>
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#include <fsl_qman.h>
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#include <fsl_bman.h>
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#include <of.h>
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#include <netcfg.h>
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#define MAX_DPAA_CORES 4
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#define DPAA_MBUF_HW_ANNOTATION 64
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#define DPAA_FD_PTA_SIZE 64
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/* mbuf->seqn will be used to store event entry index for
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* driver specific usage. For parallel mode queues, invalid
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* index will be set and for atomic mode queues, valid value
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* ranging from 1 to 16.
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*/
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#define DPAA_INVALID_MBUF_SEQN 0
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/* we will re-use the HEADROOM for annotation in RX */
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#define DPAA_HW_BUF_RESERVE 0
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#define DPAA_PACKET_LAYOUT_ALIGN 64
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/* Alignment to use for cpu-local structs to avoid coherency problems. */
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#define MAX_CACHELINE 64
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#define DPAA_MAX_RX_PKT_LEN 10240
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#define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */
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/* RX queue tail drop threshold (CGR Based) in frame count */
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#define CGR_RX_PERFQ_THRESH 256
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/*max mac filter for memac(8) including primary mac addr*/
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#define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1)
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/*Maximum number of slots available in TX ring*/
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#define DPAA_TX_BURST_SIZE 7
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/* Optimal burst size for RX and TX as default */
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#define DPAA_DEF_RX_BURST_SIZE 7
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#define DPAA_DEF_TX_BURST_SIZE DPAA_TX_BURST_SIZE
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#ifndef VLAN_TAG_SIZE
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#define VLAN_TAG_SIZE 4 /** < Vlan Header Length */
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#endif
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/* PCD frame queues */
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#define DPAA_PCD_FQID_START 0x400
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#define DPAA_PCD_FQID_MULTIPLIER 0x100
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#define DPAA_DEFAULT_NUM_PCD_QUEUES 1
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#define DPAA_MAX_NUM_PCD_QUEUES 4
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#define DPAA_IF_TX_PRIORITY 3
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#define DPAA_IF_RX_PRIORITY 0
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#define DPAA_IF_DEBUG_PRIORITY 7
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#define DPAA_IF_RX_ANNOTATION_STASH 1
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#define DPAA_IF_RX_DATA_STASH 1
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#define DPAA_IF_RX_CONTEXT_STASH 0
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/* Each "debug" FQ is represented by one of these */
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#define DPAA_DEBUG_FQ_RX_ERROR 0
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#define DPAA_DEBUG_FQ_TX_ERROR 1
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#define DPAA_RSS_OFFLOAD_ALL ( \
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ETH_RSS_FRAG_IPV4 | \
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ETH_RSS_NONFRAG_IPV4_TCP | \
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ETH_RSS_NONFRAG_IPV4_UDP | \
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ETH_RSS_NONFRAG_IPV4_SCTP | \
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ETH_RSS_FRAG_IPV6 | \
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ETH_RSS_NONFRAG_IPV6_TCP | \
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ETH_RSS_NONFRAG_IPV6_UDP | \
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ETH_RSS_NONFRAG_IPV6_SCTP)
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#define DPAA_TX_CKSUM_OFFLOAD_MASK ( \
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PKT_TX_IP_CKSUM | \
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PKT_TX_TCP_CKSUM | \
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PKT_TX_UDP_CKSUM)
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/* DPAA Frame descriptor macros */
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#define DPAA_FD_CMD_FCO 0x80000000
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/**< Frame queue Context Override */
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#define DPAA_FD_CMD_RPD 0x40000000
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/**< Read Prepended Data */
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#define DPAA_FD_CMD_UPD 0x20000000
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/**< Update Prepended Data */
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#define DPAA_FD_CMD_DTC 0x10000000
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/**< Do IP/TCP/UDP Checksum */
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#define DPAA_FD_CMD_DCL4C 0x10000000
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/**< Didn't calculate L4 Checksum */
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#define DPAA_FD_CMD_CFQ 0x00ffffff
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/**< Confirmation Frame Queue */
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/* Each network interface is represented by one of these */
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struct dpaa_if {
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int valid;
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char *name;
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const struct fm_eth_port_cfg *cfg;
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struct qman_fq *rx_queues;
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struct qman_cgr *cgr_rx;
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struct qman_fq *tx_queues;
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struct qman_fq debug_queues[2];
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uint16_t nb_rx_queues;
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uint16_t nb_tx_queues;
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uint32_t ifid;
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struct fman_if *fif;
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struct dpaa_bp_info *bp_info;
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struct rte_eth_fc_conf *fc_conf;
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};
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struct dpaa_if_stats {
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/* Rx Statistics Counter */
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uint64_t reoct; /**<Rx Eth Octets Counter */
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uint64_t roct; /**<Rx Octet Counters */
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uint64_t raln; /**<Rx Alignment Error Counter */
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uint64_t rxpf; /**<Rx valid Pause Frame */
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uint64_t rfrm; /**<Rx Frame counter */
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uint64_t rfcs; /**<Rx frame check seq error */
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uint64_t rvlan; /**<Rx Vlan Frame Counter */
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uint64_t rerr; /**<Rx Frame error */
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uint64_t ruca; /**<Rx Unicast */
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uint64_t rmca; /**<Rx Multicast */
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uint64_t rbca; /**<Rx Broadcast */
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uint64_t rdrp; /**<Rx Dropped Packet */
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uint64_t rpkt; /**<Rx packet */
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uint64_t rund; /**<Rx undersized packets */
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uint32_t res_x[14];
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uint64_t rovr; /**<Rx oversized but good */
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uint64_t rjbr; /**<Rx oversized with bad csum */
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uint64_t rfrg; /**<Rx fragment Packet */
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uint64_t rcnp; /**<Rx control packets (0x8808 */
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uint64_t rdrntp; /**<Rx dropped due to FIFO overflow */
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uint32_t res01d0[12];
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/* Tx Statistics Counter */
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uint64_t teoct; /**<Tx eth octets */
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uint64_t toct; /**<Tx Octets */
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uint32_t res0210[2];
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uint64_t txpf; /**<Tx valid pause frame */
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uint64_t tfrm; /**<Tx frame counter */
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uint64_t tfcs; /**<Tx FCS error */
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uint64_t tvlan; /**<Tx Vlan Frame */
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uint64_t terr; /**<Tx frame error */
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uint64_t tuca; /**<Tx Unicast */
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uint64_t tmca; /**<Tx Multicast */
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uint64_t tbca; /**<Tx Broadcast */
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uint32_t res0258[2];
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uint64_t tpkt; /**<Tx Packet */
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uint64_t tund; /**<Tx Undersized */
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};
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int
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dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
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int eth_rx_queue_id,
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u16 ch_id,
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const struct rte_event_eth_rx_adapter_queue_conf *queue_conf);
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int
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dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
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int eth_rx_queue_id);
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enum qman_cb_dqrr_result
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dpaa_rx_cb_parallel(void *event,
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struct qman_portal *qm __always_unused,
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struct qman_fq *fq,
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const struct qm_dqrr_entry *dqrr,
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void **bufs);
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enum qman_cb_dqrr_result
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dpaa_rx_cb_atomic(void *event,
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struct qman_portal *qm __always_unused,
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struct qman_fq *fq,
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const struct qm_dqrr_entry *dqrr,
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void **bufs);
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#endif
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