a2c6d3f34f
Add support for CPU crypto mode by introducing required handler. Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
284 lines
7.0 KiB
C
284 lines
7.0 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2015-2016 Intel Corporation
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*/
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#ifndef _AESNI_MB_PMD_PRIVATE_H_
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#define _AESNI_MB_PMD_PRIVATE_H_
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#include <intel-ipsec-mb.h>
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enum aesni_mb_vector_mode {
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RTE_AESNI_MB_NOT_SUPPORTED = 0,
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RTE_AESNI_MB_SSE,
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RTE_AESNI_MB_AVX,
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RTE_AESNI_MB_AVX2,
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RTE_AESNI_MB_AVX512
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};
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#define CRYPTODEV_NAME_AESNI_MB_PMD crypto_aesni_mb
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/**< AES-NI Multi buffer PMD device name */
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/** AESNI_MB PMD LOGTYPE DRIVER */
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extern int aesni_mb_logtype_driver;
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#define AESNI_MB_LOG(level, fmt, ...) \
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rte_log(RTE_LOG_ ## level, aesni_mb_logtype_driver, \
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"%s() line %u: " fmt "\n", __func__, __LINE__, \
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## __VA_ARGS__)
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#define HMAC_IPAD_VALUE (0x36)
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#define HMAC_OPAD_VALUE (0x5C)
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/* Maximum length for digest */
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#define DIGEST_LENGTH_MAX 64
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static const unsigned auth_blocksize[] = {
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[NULL_HASH] = 0,
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[MD5] = 64,
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[SHA1] = 64,
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[SHA_224] = 64,
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[SHA_256] = 64,
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[SHA_384] = 128,
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[SHA_512] = 128,
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[AES_XCBC] = 16,
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[AES_CCM] = 16,
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[AES_CMAC] = 16,
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[AES_GMAC] = 16,
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[PLAIN_SHA1] = 64,
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[PLAIN_SHA_224] = 64,
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[PLAIN_SHA_256] = 64,
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[PLAIN_SHA_384] = 128,
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[PLAIN_SHA_512] = 128
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};
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/**
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* Get the blocksize in bytes for a specified authentication algorithm
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*
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* @Note: this function will not return a valid value for a non-valid
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* authentication algorithm
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*/
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static inline unsigned
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get_auth_algo_blocksize(JOB_HASH_ALG algo)
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{
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return auth_blocksize[algo];
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}
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static const unsigned auth_truncated_digest_byte_lengths[] = {
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[MD5] = 12,
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[SHA1] = 12,
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[SHA_224] = 14,
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[SHA_256] = 16,
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[SHA_384] = 24,
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[SHA_512] = 32,
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[AES_XCBC] = 12,
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[AES_CMAC] = 12,
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[AES_CCM] = 8,
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[NULL_HASH] = 0,
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[AES_GMAC] = 16,
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[PLAIN_SHA1] = 20,
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[PLAIN_SHA_224] = 28,
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[PLAIN_SHA_256] = 32,
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[PLAIN_SHA_384] = 48,
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[PLAIN_SHA_512] = 64
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};
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/**
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* Get the IPsec specified truncated length in bytes of the HMAC digest for a
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* specified authentication algorithm
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*
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* @Note: this function will not return a valid value for a non-valid
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* authentication algorithm
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*/
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static inline unsigned
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get_truncated_digest_byte_length(JOB_HASH_ALG algo)
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{
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return auth_truncated_digest_byte_lengths[algo];
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}
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static const unsigned auth_digest_byte_lengths[] = {
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[MD5] = 16,
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[SHA1] = 20,
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[SHA_224] = 28,
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[SHA_256] = 32,
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[SHA_384] = 48,
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[SHA_512] = 64,
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[AES_XCBC] = 16,
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[AES_CMAC] = 16,
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[AES_CCM] = 16,
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[AES_GMAC] = 12,
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[NULL_HASH] = 0,
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[PLAIN_SHA1] = 20,
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[PLAIN_SHA_224] = 28,
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[PLAIN_SHA_256] = 32,
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[PLAIN_SHA_384] = 48,
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[PLAIN_SHA_512] = 64
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/**< Vector mode dependent pointer table of the multi-buffer APIs */
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};
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/**
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* Get the full digest size in bytes for a specified authentication algorithm
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* (if available in the Multi-buffer library)
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*
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* @Note: this function will not return a valid value for a non-valid
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* authentication algorithm
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*/
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static inline unsigned
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get_digest_byte_length(JOB_HASH_ALG algo)
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{
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return auth_digest_byte_lengths[algo];
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}
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enum aesni_mb_operation {
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AESNI_MB_OP_HASH_CIPHER,
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AESNI_MB_OP_CIPHER_HASH,
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AESNI_MB_OP_HASH_ONLY,
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AESNI_MB_OP_CIPHER_ONLY,
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AESNI_MB_OP_AEAD_HASH_CIPHER,
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AESNI_MB_OP_AEAD_CIPHER_HASH,
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AESNI_MB_OP_NOT_SUPPORTED
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};
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/** private data structure for each virtual AESNI device */
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struct aesni_mb_private {
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enum aesni_mb_vector_mode vector_mode;
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/**< CPU vector instruction set mode */
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unsigned max_nb_queue_pairs;
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/**< Max number of queue pairs supported by device */
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MB_MGR *mb_mgr;
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/**< Multi-buffer instance */
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};
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/** AESNI Multi buffer queue pair */
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struct aesni_mb_qp {
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uint16_t id;
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/**< Queue Pair Identifier */
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char name[RTE_CRYPTODEV_NAME_MAX_LEN];
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/**< Unique Queue Pair Name */
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MB_MGR *mb_mgr;
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/**< Multi-buffer instance */
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struct rte_ring *ingress_queue;
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/**< Ring for placing operations ready for processing */
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struct rte_mempool *sess_mp;
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/**< Session Mempool */
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struct rte_mempool *sess_mp_priv;
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/**< Session Private Data Mempool */
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struct rte_cryptodev_stats stats;
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/**< Queue pair statistics */
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uint8_t digest_idx;
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/**< Index of the next slot to be used in temp_digests,
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* to store the digest for a given operation
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*/
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uint8_t temp_digests[MAX_JOBS][DIGEST_LENGTH_MAX];
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/**< Buffers used to store the digest generated
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* by the driver when verifying a digest provided
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* by the user (using authentication verify operation)
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*/
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} __rte_cache_aligned;
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/** AES-NI multi-buffer private session structure */
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struct aesni_mb_session {
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JOB_CHAIN_ORDER chain_order;
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struct {
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uint16_t length;
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uint16_t offset;
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} iv;
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/**< IV parameters */
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/** Cipher Parameters */const struct aesni_mb_op_fns *op_fns;
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/**< Vector mode dependent pointer table of the multi-buffer APIs */
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struct {
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/** Cipher direction - encrypt / decrypt */
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JOB_CIPHER_DIRECTION direction;
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/** Cipher mode - CBC / Counter */
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JOB_CIPHER_MODE mode;
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uint64_t key_length_in_bytes;
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union {
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struct {
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uint32_t encode[60] __rte_aligned(16);
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/**< encode key */
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uint32_t decode[60] __rte_aligned(16);
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/**< decode key */
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} expanded_aes_keys;
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struct {
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const void *ks_ptr[3];
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uint64_t key[3][16];
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} exp_3des_keys;
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struct gcm_key_data gcm_key;
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};
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/**< Expanded AES keys - Allocating space to
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* contain the maximum expanded key size which
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* is 240 bytes for 256 bit AES, calculate by:
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* ((key size (bytes)) *
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* ((number of rounds) + 1))
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*/
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} cipher;
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/** Authentication Parameters */
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struct {
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JOB_HASH_ALG algo; /**< Authentication Algorithm */
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enum rte_crypto_auth_operation operation;
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/**< auth operation generate or verify */
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union {
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struct {
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uint8_t inner[128] __rte_aligned(16);
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/**< inner pad */
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uint8_t outer[128] __rte_aligned(16);
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/**< outer pad */
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} pads;
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/**< HMAC Authentication pads -
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* allocating space for the maximum pad
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* size supported which is 128 bytes for
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* SHA512
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*/
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struct {
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uint32_t k1_expanded[44] __rte_aligned(16);
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/**< k1 (expanded key). */
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uint8_t k2[16] __rte_aligned(16);
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/**< k2. */
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uint8_t k3[16] __rte_aligned(16);
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/**< k3. */
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} xcbc;
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struct {
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uint32_t expkey[60] __rte_aligned(16);
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/**< k1 (expanded key). */
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uint32_t skey1[4] __rte_aligned(16);
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/**< k2. */
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uint32_t skey2[4] __rte_aligned(16);
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/**< k3. */
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} cmac;
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/**< Expanded XCBC authentication keys */
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};
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/** Generated digest size by the Multi-buffer library */
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uint16_t gen_digest_len;
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/** Requested digest size from Cryptodev */
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uint16_t req_digest_len;
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} auth;
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struct {
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/** AAD data length */
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uint16_t aad_len;
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} aead;
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} __rte_cache_aligned;
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extern int
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aesni_mb_set_session_parameters(const MB_MGR *mb_mgr,
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struct aesni_mb_session *sess,
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const struct rte_crypto_sym_xform *xform);
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/** device specific operations function pointer structure */
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extern struct rte_cryptodev_ops *rte_aesni_mb_pmd_ops;
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extern uint32_t
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aesni_mb_cpu_crypto_process_bulk(struct rte_cryptodev *dev,
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struct rte_cryptodev_sym_session *sess, union rte_crypto_sym_ofs sofs,
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struct rte_crypto_sym_vec *vec);
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#endif /* _AESNI_MB_PMD_PRIVATE_H_ */
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