c13cecf60f
This patch implements a special way of buffer handling when internal QAT IM buffer is too small for Huffman dynamic compression operation. Instead of falling back to fixed compression, the operation is now split into multiple smaller dynamic compression requests (possible to execute on QAT) and their results are then combined and copied into the output buffer. This is not possible if any checksum calculation was requested - in such case the code falls back to fixed compression as before. Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com> Acked-by: Fiona Trahe <fiona.trahe@intel.com>
144 lines
3.5 KiB
C
144 lines
3.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2015-2019 Intel Corporation
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*/
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#ifndef _QAT_COMP_H_
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#define _QAT_COMP_H_
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#ifdef RTE_LIBRTE_COMPRESSDEV
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#include <rte_compressdev.h>
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#include <rte_compressdev_pmd.h>
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#include "qat_common.h"
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#include "qat_qp.h"
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#include "icp_qat_hw.h"
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#include "icp_qat_fw_comp.h"
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#include "icp_qat_fw_la.h"
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#define QAT_64_BYTE_ALIGN_MASK (~0x3f)
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#define QAT_64_BYTE_ALIGN (64)
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#define QAT_NUM_BUFS_IN_IM_SGL 1
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#define ERR_CODE_QAT_COMP_WRONG_FW -99
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/* fallback to fixed compression threshold */
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#define QAT_FALLBACK_THLD ((uint32_t)(RTE_PMD_QAT_COMP_IM_BUFFER_SIZE / 1.3))
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#define QAT_MIN_OUT_BUF_SIZE 46
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/* maximum size of the state registers */
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#define QAT_STATE_REGISTERS_MAX_SIZE 64
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/* decompressor context size */
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#define QAT_INFLATE_CONTEXT_SIZE_GEN1 36864
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#define QAT_INFLATE_CONTEXT_SIZE_GEN2 34032
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#define QAT_INFLATE_CONTEXT_SIZE_GEN3 34032
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#define QAT_INFLATE_CONTEXT_SIZE RTE_MAX(RTE_MAX(QAT_INFLATE_CONTEXT_SIZE_GEN1,\
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QAT_INFLATE_CONTEXT_SIZE_GEN2), QAT_INFLATE_CONTEXT_SIZE_GEN3)
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enum qat_comp_request_type {
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QAT_COMP_REQUEST_FIXED_COMP_STATELESS,
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QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS,
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QAT_COMP_REQUEST_DECOMPRESS,
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REQ_COMP_END
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};
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struct array_of_ptrs {
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phys_addr_t pointer[0];
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};
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struct qat_inter_sgl {
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qat_sgl_hdr;
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struct qat_flat_buf buffers[QAT_NUM_BUFS_IN_IM_SGL];
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} __rte_packed __rte_cache_aligned;
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struct qat_comp_op_cookie {
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phys_addr_t qat_sgl_src_phys_addr;
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phys_addr_t qat_sgl_dst_phys_addr;
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/* dynamically created SGLs */
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uint8_t error;
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uint8_t socket_id;
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uint16_t src_nb_elems;
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uint16_t dst_nb_elems;
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struct qat_sgl *qat_sgl_src_d;
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struct qat_sgl *qat_sgl_dst_d;
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struct qat_qp *qp;
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uint32_t cookie_index;
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/* QAT IM buffer too small handling: */
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uint8_t split_op;
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uint8_t nb_children;
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/* used by the parent only */
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uint8_t nb_child_responses;
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uint32_t total_consumed;
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uint32_t total_produced;
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const struct rte_memzone **dst_memzones;
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struct rte_mbuf *dst_data;
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uint32_t dst_data_offset;
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/* used by the child only */
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struct qat_comp_op_cookie *parent_cookie;
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void *dest_buffer;
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};
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struct qat_comp_xform {
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struct icp_qat_fw_comp_req qat_comp_req_tmpl;
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enum qat_comp_request_type qat_comp_request_type;
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enum rte_comp_checksum_type checksum_type;
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};
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struct qat_comp_stream {
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struct qat_comp_xform qat_xform;
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void *state_registers_decomp;
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phys_addr_t state_registers_decomp_phys;
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void *inflate_context;
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phys_addr_t inflate_context_phys;
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const struct rte_memzone *memzone;
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uint8_t start_of_packet;
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volatile uint8_t op_in_progress;
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};
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int
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qat_comp_build_request(void *in_op, uint8_t *out_msg, void *op_cookie,
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enum qat_device_gen qat_dev_gen __rte_unused);
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int
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qat_comp_build_multiple_requests(void *in_op, struct qat_qp *qp,
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uint32_t parent_tail, int nb_descr);
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void
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qat_comp_free_split_op_memzones(struct qat_comp_op_cookie *cookie,
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unsigned int nb_children);
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int
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qat_comp_process_response(void **op, uint8_t *resp, void *op_cookie,
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uint64_t *dequeue_err_count);
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int
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qat_comp_private_xform_create(struct rte_compressdev *dev,
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const struct rte_comp_xform *xform,
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void **private_xform);
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int
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qat_comp_private_xform_free(struct rte_compressdev *dev, void *private_xform);
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unsigned int
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qat_comp_xform_size(void);
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unsigned int
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qat_comp_stream_size(void);
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int
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qat_comp_stream_create(struct rte_compressdev *dev,
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const struct rte_comp_xform *xform,
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void **stream);
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int
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qat_comp_stream_free(struct rte_compressdev *dev, void *stream);
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#endif
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#endif
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