902f389f9b
Shifting signed 32-bit values by 31-bits has the potential for unexpected outcomes as compiler can overwrite a bit. Specified that values are unsigned. Errors are observed from running cppcheck. Bugzilla ID: 58 Fixes:69e209be54("net/axgbe: add register map and related macros") Fixes:b5bf771922("bnx2x: driver support routines") Fixes:ed2ced6fe9("net/bnxt: check initialization before accessing stats") Fixes:6fda3f0ddd("net/cxgbe: add API to program hardware MPS table") Fixes:bdb244b969("e1000: whitespace changes") Fixes:5a32a257f9("e1000: more NICs in base driver") Fixes:2fe669f4bc("net/nfp: support MAC address change") Fixes:defb9a5dd1("nfp: introduce driver initialization") Fixes:ec94dbc573("qede: add base driver") Fixes:d2e7d931d0("net/qede/base: formatting changes") Fixes:cdc07e83bb("net/tap: add eBPF program file") Cc: stable@dpdk.org Signed-off-by: Andrius Sirvys <andrius.sirvys@intel.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
353 lines
16 KiB
C
353 lines
16 KiB
C
/*
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* Copyright (c) 2014, 2015 Netronome Systems, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* vim:shiftwidth=8:noexpandtab
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*
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* Netronome network device driver: Control BAR layout
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*/
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#ifndef _NFP_NET_CTRL_H_
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#define _NFP_NET_CTRL_H_
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/*
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* Configuration BAR size.
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*
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* The configuration BAR is 8K in size, but on the NFP6000, due to
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* THB-350, 32k needs to be reserved.
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*/
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#ifdef __NFP_IS_6000
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#define NFP_NET_CFG_BAR_SZ (32 * 1024)
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#else
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#define NFP_NET_CFG_BAR_SZ (8 * 1024)
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#endif
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/* Offset in Freelist buffer where packet starts on RX */
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#define NFP_NET_RX_OFFSET 32
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/* working with metadata api (NFD version > 3.0) */
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#define NFP_NET_META_FIELD_SIZE 4
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#define NFP_NET_META_FIELD_MASK ((1 << NFP_NET_META_FIELD_SIZE) - 1)
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/* Prepend field types */
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#define NFP_NET_META_HASH 1 /* next field carries hash type */
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/* Hash type pre-pended when a RSS hash was computed */
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#define NFP_NET_RSS_NONE 0
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#define NFP_NET_RSS_IPV4 1
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#define NFP_NET_RSS_IPV6 2
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#define NFP_NET_RSS_IPV6_EX 3
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#define NFP_NET_RSS_IPV4_TCP 4
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#define NFP_NET_RSS_IPV6_TCP 5
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#define NFP_NET_RSS_IPV6_EX_TCP 6
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#define NFP_NET_RSS_IPV4_UDP 7
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#define NFP_NET_RSS_IPV6_UDP 8
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#define NFP_NET_RSS_IPV6_EX_UDP 9
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/*
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* @NFP_NET_TXR_MAX: Maximum number of TX rings
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* @NFP_NET_TXR_MASK: Mask for TX rings
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* @NFP_NET_RXR_MAX: Maximum number of RX rings
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* @NFP_NET_RXR_MASK: Mask for RX rings
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*/
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#define NFP_NET_TXR_MAX 64
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#define NFP_NET_TXR_MASK (NFP_NET_TXR_MAX - 1)
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#define NFP_NET_RXR_MAX 64
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#define NFP_NET_RXR_MASK (NFP_NET_RXR_MAX - 1)
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/*
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* Read/Write config words (0x0000 - 0x002c)
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* @NFP_NET_CFG_CTRL: Global control
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* @NFP_NET_CFG_UPDATE: Indicate which fields are updated
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* @NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings
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* @NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings
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* @NFP_NET_CFG_MTU: Set MTU size
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* @NFP_NET_CFG_FLBUFSZ: Set freelist buffer size (must be larger than MTU)
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* @NFP_NET_CFG_EXN: MSI-X table entry for exceptions
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* @NFP_NET_CFG_LSC: MSI-X table entry for link state changes
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* @NFP_NET_CFG_MACADDR: MAC address
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*
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* TODO:
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* - define Error details in UPDATE
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*/
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#define NFP_NET_CFG_CTRL 0x0000
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#define NFP_NET_CFG_CTRL_ENABLE (0x1 << 0) /* Global enable */
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#define NFP_NET_CFG_CTRL_PROMISC (0x1 << 1) /* Enable Promisc mode */
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#define NFP_NET_CFG_CTRL_L2BC (0x1 << 2) /* Allow L2 Broadcast */
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#define NFP_NET_CFG_CTRL_L2MC (0x1 << 3) /* Allow L2 Multicast */
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#define NFP_NET_CFG_CTRL_RXCSUM (0x1 << 4) /* Enable RX Checksum */
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#define NFP_NET_CFG_CTRL_TXCSUM (0x1 << 5) /* Enable TX Checksum */
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#define NFP_NET_CFG_CTRL_RXVLAN (0x1 << 6) /* Enable VLAN strip */
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#define NFP_NET_CFG_CTRL_TXVLAN (0x1 << 7) /* Enable VLAN insert */
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#define NFP_NET_CFG_CTRL_SCATTER (0x1 << 8) /* Scatter DMA */
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#define NFP_NET_CFG_CTRL_GATHER (0x1 << 9) /* Gather DMA */
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#define NFP_NET_CFG_CTRL_LSO (0x1 << 10) /* LSO/TSO */
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#define NFP_NET_CFG_CTRL_RINGCFG (0x1 << 16) /* Ring runtime changes */
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#define NFP_NET_CFG_CTRL_RSS (0x1 << 17) /* RSS */
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#define NFP_NET_CFG_CTRL_IRQMOD (0x1 << 18) /* Interrupt moderation */
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#define NFP_NET_CFG_CTRL_RINGPRIO (0x1 << 19) /* Ring priorities */
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#define NFP_NET_CFG_CTRL_MSIXAUTO (0x1 << 20) /* MSI-X auto-masking */
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#define NFP_NET_CFG_CTRL_TXRWB (0x1 << 21) /* Write-back of TX ring*/
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#define NFP_NET_CFG_CTRL_L2SWITCH (0x1 << 22) /* L2 Switch */
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#define NFP_NET_CFG_CTRL_L2SWITCH_LOCAL (0x1 << 23) /* Switch to local */
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#define NFP_NET_CFG_CTRL_VXLAN (0x1 << 24) /* Enable VXLAN */
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#define NFP_NET_CFG_CTRL_NVGRE (0x1 << 25) /* Enable NVGRE */
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#define NFP_NET_CFG_CTRL_MSIX_TX_OFF (0x1 << 26) /* Disable MSIX for TX */
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#define NFP_NET_CFG_CTRL_LSO2 (0x1 << 28) /* LSO/TSO (version 2) */
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#define NFP_NET_CFG_CTRL_RSS2 (0x1 << 29) /* RSS (version 2) */
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#define NFP_NET_CFG_CTRL_LIVE_ADDR (0x1U << 31)/* live MAC addr change */
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#define NFP_NET_CFG_UPDATE 0x0004
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#define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */
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#define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */
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#define NFP_NET_CFG_UPDATE_RSS (0x1 << 2) /* RSS config change */
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#define NFP_NET_CFG_UPDATE_TXRPRIO (0x1 << 3) /* TX Ring prio change */
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#define NFP_NET_CFG_UPDATE_RXRPRIO (0x1 << 4) /* RX Ring prio change */
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#define NFP_NET_CFG_UPDATE_MSIX (0x1 << 5) /* MSI-X change */
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#define NFP_NET_CFG_UPDATE_L2SWITCH (0x1 << 6) /* Switch changes */
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#define NFP_NET_CFG_UPDATE_RESET (0x1 << 7) /* Update due to FLR */
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#define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */
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#define NFP_NET_CFG_UPDATE_VXLAN (0x1 << 9) /* VXLAN port change */
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#define NFP_NET_CFG_UPDATE_MACADDR (0x1 << 11) /* MAC address change */
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#define NFP_NET_CFG_UPDATE_ERR (0x1U << 31) /* A error occurred */
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#define NFP_NET_CFG_TXRS_ENABLE 0x0008
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#define NFP_NET_CFG_RXRS_ENABLE 0x0010
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#define NFP_NET_CFG_MTU 0x0018
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#define NFP_NET_CFG_FLBUFSZ 0x001c
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#define NFP_NET_CFG_EXN 0x001f
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#define NFP_NET_CFG_LSC 0x0020
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#define NFP_NET_CFG_MACADDR 0x0024
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#define NFP_NET_CFG_CTRL_LSO_ANY (NFP_NET_CFG_CTRL_LSO | NFP_NET_CFG_CTRL_LSO2)
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/*
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* Read-only words (0x0030 - 0x0050):
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* @NFP_NET_CFG_VERSION: Firmware version number
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* @NFP_NET_CFG_STS: Status
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* @NFP_NET_CFG_CAP: Capabilities (same bits as @NFP_NET_CFG_CTRL)
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* @NFP_NET_MAX_TXRINGS: Maximum number of TX rings
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* @NFP_NET_MAX_RXRINGS: Maximum number of RX rings
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* @NFP_NET_MAX_MTU: Maximum support MTU
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* @NFP_NET_CFG_START_TXQ: Start Queue Control Queue to use for TX (PF only)
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* @NFP_NET_CFG_START_RXQ: Start Queue Control Queue to use for RX (PF only)
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*
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* TODO:
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* - define more STS bits
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*/
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#define NFP_NET_CFG_VERSION 0x0030
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#define NFP_NET_CFG_VERSION_RESERVED_MASK (0xff << 24)
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#define NFP_NET_CFG_VERSION_CLASS_MASK (0xff << 16)
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#define NFP_NET_CFG_VERSION_CLASS(x) (((x) & 0xff) << 16)
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#define NFP_NET_CFG_VERSION_CLASS_GENERIC 0
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#define NFP_NET_CFG_VERSION_MAJOR_MASK (0xff << 8)
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#define NFP_NET_CFG_VERSION_MAJOR(x) (((x) & 0xff) << 8)
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#define NFP_NET_CFG_VERSION_MINOR_MASK (0xff << 0)
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#define NFP_NET_CFG_VERSION_MINOR(x) (((x) & 0xff) << 0)
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#define NFP_NET_CFG_STS 0x0034
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#define NFP_NET_CFG_STS_LINK (0x1 << 0) /* Link up or down */
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/* Link rate */
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#define NFP_NET_CFG_STS_LINK_RATE_SHIFT 1
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#define NFP_NET_CFG_STS_LINK_RATE_MASK 0xF
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#define NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED 0
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#define NFP_NET_CFG_STS_LINK_RATE_UNKNOWN 1
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#define NFP_NET_CFG_STS_LINK_RATE_1G 2
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#define NFP_NET_CFG_STS_LINK_RATE_10G 3
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#define NFP_NET_CFG_STS_LINK_RATE_25G 4
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#define NFP_NET_CFG_STS_LINK_RATE_40G 5
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#define NFP_NET_CFG_STS_LINK_RATE_50G 6
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#define NFP_NET_CFG_STS_LINK_RATE_100G 7
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#define NFP_NET_CFG_CAP 0x0038
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#define NFP_NET_CFG_MAX_TXRINGS 0x003c
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#define NFP_NET_CFG_MAX_RXRINGS 0x0040
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#define NFP_NET_CFG_MAX_MTU 0x0044
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/* Next two words are being used by VFs for solving THB350 issue */
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#define NFP_NET_CFG_START_TXQ 0x0048
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#define NFP_NET_CFG_START_RXQ 0x004c
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/*
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* NFP-3200 workaround (0x0050 - 0x0058)
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* @NFP_NET_CFG_SPARE_ADDR: DMA address for ME code to use (e.g. YDS-155 fix)
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*/
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#define NFP_NET_CFG_SPARE_ADDR 0x0050
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/**
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* NFP6000/NFP4000 - Prepend configuration
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*/
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#define NFP_NET_CFG_RX_OFFSET 0x0050
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#define NFP_NET_CFG_RX_OFFSET_DYNAMIC 0 /* Prepend mode */
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/**
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* Reuse spare address to contain the offset from the start of
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* the host buffer where the first byte of the received frame
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* will land. Any metadata will come prior to that offset. If the
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* value in this field is 0, it means that that the metadata will
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* always land starting at the first byte of the host buffer and
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* packet data will immediately follow the metadata. As always,
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* the RX descriptor indicates the presence or absence of metadata
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* along with the length thereof.
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*/
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#define NFP_NET_CFG_RX_OFFSET_ADDR 0x0050
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#define NFP_NET_CFG_VXLAN_PORT 0x0060
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#define NFP_NET_CFG_VXLAN_SZ 0x0008
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/* Offload definitions */
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#define NFP_NET_N_VXLAN_PORTS (NFP_NET_CFG_VXLAN_SZ / sizeof(uint16_t))
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/**
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* 64B reserved for future use (0x0080 - 0x00c0)
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*/
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#define NFP_NET_CFG_RESERVED 0x0080
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#define NFP_NET_CFG_RESERVED_SZ 0x0040
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/*
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* RSS configuration (0x0100 - 0x01ac):
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* Used only when NFP_NET_CFG_CTRL_RSS is enabled
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* @NFP_NET_CFG_RSS_CFG: RSS configuration word
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* @NFP_NET_CFG_RSS_KEY: RSS "secret" key
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* @NFP_NET_CFG_RSS_ITBL: RSS indirection table
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*/
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#define NFP_NET_CFG_RSS_BASE 0x0100
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#define NFP_NET_CFG_RSS_CTRL NFP_NET_CFG_RSS_BASE
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#define NFP_NET_CFG_RSS_MASK (0x7f)
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#define NFP_NET_CFG_RSS_MASK_of(_x) ((_x) & 0x7f)
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#define NFP_NET_CFG_RSS_IPV4 (1 << 8) /* RSS for IPv4 */
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#define NFP_NET_CFG_RSS_IPV6 (1 << 9) /* RSS for IPv6 */
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#define NFP_NET_CFG_RSS_IPV4_TCP (1 << 10) /* RSS for IPv4/TCP */
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#define NFP_NET_CFG_RSS_IPV4_UDP (1 << 11) /* RSS for IPv4/UDP */
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#define NFP_NET_CFG_RSS_IPV6_TCP (1 << 12) /* RSS for IPv6/TCP */
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#define NFP_NET_CFG_RSS_IPV6_UDP (1 << 13) /* RSS for IPv6/UDP */
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#define NFP_NET_CFG_RSS_TOEPLITZ (1 << 24) /* Use Toeplitz hash */
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#define NFP_NET_CFG_RSS_KEY (NFP_NET_CFG_RSS_BASE + 0x4)
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#define NFP_NET_CFG_RSS_KEY_SZ 0x28
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#define NFP_NET_CFG_RSS_ITBL (NFP_NET_CFG_RSS_BASE + 0x4 + \
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NFP_NET_CFG_RSS_KEY_SZ)
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#define NFP_NET_CFG_RSS_ITBL_SZ 0x80
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/*
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* TX ring configuration (0x200 - 0x800)
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* @NFP_NET_CFG_TXR_BASE: Base offset for TX ring configuration
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* @NFP_NET_CFG_TXR_ADDR: Per TX ring DMA address (8B entries)
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* @NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries)
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* @NFP_NET_CFG_TXR_SZ: Per TX ring ring size (1B entries)
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* @NFP_NET_CFG_TXR_VEC: Per TX ring MSI-X table entry (1B entries)
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* @NFP_NET_CFG_TXR_PRIO: Per TX ring priority (1B entries)
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* @NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation (4B entries)
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*/
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#define NFP_NET_CFG_TXR_BASE 0x0200
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#define NFP_NET_CFG_TXR_ADDR(_x) (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8))
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#define NFP_NET_CFG_TXR_WB_ADDR(_x) (NFP_NET_CFG_TXR_BASE + 0x200 + \
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((_x) * 0x8))
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#define NFP_NET_CFG_TXR_SZ(_x) (NFP_NET_CFG_TXR_BASE + 0x400 + (_x))
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#define NFP_NET_CFG_TXR_VEC(_x) (NFP_NET_CFG_TXR_BASE + 0x440 + (_x))
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#define NFP_NET_CFG_TXR_PRIO(_x) (NFP_NET_CFG_TXR_BASE + 0x480 + (_x))
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#define NFP_NET_CFG_TXR_IRQ_MOD(_x) (NFP_NET_CFG_TXR_BASE + 0x500 + \
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((_x) * 0x4))
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/*
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* RX ring configuration (0x0800 - 0x0c00)
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* @NFP_NET_CFG_RXR_BASE: Base offset for RX ring configuration
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* @NFP_NET_CFG_RXR_ADDR: Per TX ring DMA address (8B entries)
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* @NFP_NET_CFG_RXR_SZ: Per TX ring ring size (1B entries)
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* @NFP_NET_CFG_RXR_VEC: Per TX ring MSI-X table entry (1B entries)
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* @NFP_NET_CFG_RXR_PRIO: Per TX ring priority (1B entries)
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* @NFP_NET_CFG_RXR_IRQ_MOD: Per TX ring interrupt moderation (4B entries)
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*/
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#define NFP_NET_CFG_RXR_BASE 0x0800
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#define NFP_NET_CFG_RXR_ADDR(_x) (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8))
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#define NFP_NET_CFG_RXR_SZ(_x) (NFP_NET_CFG_RXR_BASE + 0x200 + (_x))
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#define NFP_NET_CFG_RXR_VEC(_x) (NFP_NET_CFG_RXR_BASE + 0x240 + (_x))
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#define NFP_NET_CFG_RXR_PRIO(_x) (NFP_NET_CFG_RXR_BASE + 0x280 + (_x))
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#define NFP_NET_CFG_RXR_IRQ_MOD(_x) (NFP_NET_CFG_RXR_BASE + 0x300 + \
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((_x) * 0x4))
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/*
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* Interrupt Control/Cause registers (0x0c00 - 0x0d00)
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* These registers are only used when MSI-X auto-masking is not
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* enabled (@NFP_NET_CFG_CTRL_MSIXAUTO not set). The array is index
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* by MSI-X entry and are 1B in size. If an entry is zero, the
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* corresponding entry is enabled. If the FW generates an interrupt,
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* it writes a cause into the corresponding field. This also masks
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* the MSI-X entry and the host driver must clear the register to
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* re-enable the interrupt.
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*/
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#define NFP_NET_CFG_ICR_BASE 0x0c00
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#define NFP_NET_CFG_ICR(_x) (NFP_NET_CFG_ICR_BASE + (_x))
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#define NFP_NET_CFG_ICR_UNMASKED 0x0
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#define NFP_NET_CFG_ICR_RXTX 0x1
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#define NFP_NET_CFG_ICR_LSC 0x2
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/*
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* General device stats (0x0d00 - 0x0d90)
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* all counters are 64bit.
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*/
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#define NFP_NET_CFG_STATS_BASE 0x0d00
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#define NFP_NET_CFG_STATS_RX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x00)
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#define NFP_NET_CFG_STATS_RX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x08)
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#define NFP_NET_CFG_STATS_RX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x10)
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#define NFP_NET_CFG_STATS_RX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x18)
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#define NFP_NET_CFG_STATS_RX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x20)
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#define NFP_NET_CFG_STATS_RX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x28)
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#define NFP_NET_CFG_STATS_RX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x30)
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#define NFP_NET_CFG_STATS_RX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x38)
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#define NFP_NET_CFG_STATS_RX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x40)
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#define NFP_NET_CFG_STATS_TX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x48)
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#define NFP_NET_CFG_STATS_TX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x50)
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#define NFP_NET_CFG_STATS_TX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x58)
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#define NFP_NET_CFG_STATS_TX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x60)
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#define NFP_NET_CFG_STATS_TX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x68)
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#define NFP_NET_CFG_STATS_TX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x70)
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#define NFP_NET_CFG_STATS_TX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x78)
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#define NFP_NET_CFG_STATS_TX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x80)
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#define NFP_NET_CFG_STATS_TX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x88)
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/*
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* Per ring stats (0x1000 - 0x1800)
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* options, 64bit per entry
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* @NFP_NET_CFG_TXR_STATS: TX ring statistics (Packet and Byte count)
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* @NFP_NET_CFG_RXR_STATS: RX ring statistics (Packet and Byte count)
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*/
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#define NFP_NET_CFG_TXR_STATS_BASE 0x1000
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#define NFP_NET_CFG_TXR_STATS(_x) (NFP_NET_CFG_TXR_STATS_BASE + \
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((_x) * 0x10))
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#define NFP_NET_CFG_RXR_STATS_BASE 0x1400
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#define NFP_NET_CFG_RXR_STATS(_x) (NFP_NET_CFG_RXR_STATS_BASE + \
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((_x) * 0x10))
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/* PF multiport offset */
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#define NFP_PF_CSR_SLICE_SIZE (32 * 1024)
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#endif /* _NFP_NET_CTRL_H_ */
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/*
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* Local variables:
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* c-file-style: "Linux"
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* indent-tabs-mode: t
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* End:
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*/
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