c82dd0a7bf
1. Add fm10k_recv_scattered_pkts function to receive jumbo frame and multi-segment packets. 2. Configure correct receive function in rx_init and dev_init. Signed-off-by: Jeff Shaw <jeffrey.b.shaw@intel.com> Signed-off-by: Chen Jing D(Mark) <jing.d.chen@intel.com>
293 lines
9.1 KiB
C
293 lines
9.1 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _FM10K_H_
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#define _FM10K_H_
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#include <stdint.h>
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#include <rte_mbuf.h>
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#include <rte_mempool.h>
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#include <rte_malloc.h>
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#include <rte_spinlock.h>
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#include "fm10k_logs.h"
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#include "base/fm10k_type.h"
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/* descriptor ring base addresses must be aligned to the following */
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#define FM10K_ALIGN_RX_DESC 128
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#define FM10K_ALIGN_TX_DESC 128
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/* The maximum packet size that FM10K supports */
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#define FM10K_MAX_PKT_SIZE (15 * 1024)
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/* Minimum size of RX buffer FM10K supported */
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#define FM10K_MIN_RX_BUF_SIZE 256
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/* The maximum of SRIOV VFs per port supported */
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#define FM10K_MAX_VF_NUM 64
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/* number of descriptors must be a multiple of the following */
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#define FM10K_MULT_RX_DESC FM10K_REQ_RX_DESCRIPTOR_MULTIPLE
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#define FM10K_MULT_TX_DESC FM10K_REQ_TX_DESCRIPTOR_MULTIPLE
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/* maximum size of descriptor rings */
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#define FM10K_MAX_RX_RING_SZ (512 * 1024)
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#define FM10K_MAX_TX_RING_SZ (512 * 1024)
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/* minimum and maximum number of descriptors in a ring */
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#define FM10K_MIN_RX_DESC 32
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#define FM10K_MIN_TX_DESC 32
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#define FM10K_MAX_RX_DESC (FM10K_MAX_RX_RING_SZ / sizeof(union fm10k_rx_desc))
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#define FM10K_MAX_TX_DESC (FM10K_MAX_TX_RING_SZ / sizeof(struct fm10k_tx_desc))
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/*
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* byte aligment for HW RX data buffer
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* Datasheet requires RX buffer addresses shall either be 512-byte aligned or
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* be 8-byte aligned but without crossing host memory pages (4KB alignment
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* boundaries). Satisfy first option.
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*/
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#define FM10K_RX_DATABUF_ALIGN 512
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/*
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* threshold default, min, max, and divisor constraints
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* the configured values must satisfy the following:
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* MIN <= value <= MAX
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* DIV % value == 0
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*/
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#define FM10K_RX_FREE_THRESH_DEFAULT(rxq) 32
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#define FM10K_RX_FREE_THRESH_MIN(rxq) 1
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#define FM10K_RX_FREE_THRESH_MAX(rxq) ((rxq)->nb_desc - 1)
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#define FM10K_RX_FREE_THRESH_DIV(rxq) ((rxq)->nb_desc)
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#define FM10K_TX_FREE_THRESH_DEFAULT(txq) 32
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#define FM10K_TX_FREE_THRESH_MIN(txq) 1
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#define FM10K_TX_FREE_THRESH_MAX(txq) ((txq)->nb_desc - 3)
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#define FM10K_TX_FREE_THRESH_DIV(txq) 0
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#define FM10K_DEFAULT_RX_PTHRESH 8
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#define FM10K_DEFAULT_RX_HTHRESH 8
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#define FM10K_DEFAULT_RX_WTHRESH 0
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#define FM10K_DEFAULT_TX_PTHRESH 32
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#define FM10K_DEFAULT_TX_HTHRESH 0
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#define FM10K_DEFAULT_TX_WTHRESH 0
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#define FM10K_TX_RS_THRESH_DEFAULT(txq) 32
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#define FM10K_TX_RS_THRESH_MIN(txq) 1
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#define FM10K_TX_RS_THRESH_MAX(txq) \
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RTE_MIN(((txq)->nb_desc - 2), (txq)->free_thresh)
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#define FM10K_TX_RS_THRESH_DIV(txq) ((txq)->nb_desc)
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#define FM10K_VLAN_TAG_SIZE 4
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struct fm10k_dev_info {
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volatile uint32_t enable;
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volatile uint32_t glort;
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/* Protect the mailbox to avoid race condition */
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rte_spinlock_t mbx_lock;
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};
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/*
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* Structure to store private data for each driver instance.
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*/
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struct fm10k_adapter {
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struct fm10k_hw hw;
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struct fm10k_hw_stats stats;
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struct fm10k_dev_info info;
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};
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#define FM10K_DEV_PRIVATE_TO_HW(adapter) \
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(&((struct fm10k_adapter *)adapter)->hw)
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#define FM10K_DEV_PRIVATE_TO_STATS(adapter) \
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(&((struct fm10k_adapter *)adapter)->stats)
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#define FM10K_DEV_PRIVATE_TO_INFO(adapter) \
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(&((struct fm10k_adapter *)adapter)->info)
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#define FM10K_DEV_PRIVATE_TO_MBXLOCK(adapter) \
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(&(((struct fm10k_adapter *)adapter)->info.mbx_lock))
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struct fm10k_rx_queue {
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struct rte_mempool *mp;
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struct rte_mbuf **sw_ring;
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volatile union fm10k_rx_desc *hw_ring;
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struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
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struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
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uint64_t hw_ring_phys_addr;
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uint16_t next_dd;
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uint16_t next_alloc;
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uint16_t next_trigger;
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uint16_t alloc_thresh;
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volatile uint32_t *tail_ptr;
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uint16_t nb_desc;
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uint16_t queue_id;
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uint8_t port_id;
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uint8_t drop_en;
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uint8_t rx_deferred_start; /**< don't start this queue in dev start. */
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};
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/*
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* a FIFO is used to track which descriptors have their RS bit set for Tx
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* queues which are configured to allow multiple descriptors per packet
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*/
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struct fifo {
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uint16_t *list;
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uint16_t *head;
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uint16_t *tail;
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uint16_t *endp;
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};
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struct fm10k_tx_queue {
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struct rte_mbuf **sw_ring;
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struct fm10k_tx_desc *hw_ring;
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uint64_t hw_ring_phys_addr;
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struct fifo rs_tracker;
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uint16_t last_free;
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uint16_t next_free;
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uint16_t nb_free;
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uint16_t nb_used;
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uint16_t free_trigger;
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uint16_t free_thresh;
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uint16_t rs_thresh;
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volatile uint32_t *tail_ptr;
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uint16_t nb_desc;
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uint8_t port_id;
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uint8_t tx_deferred_start; /** < don't start this queue in dev start. */
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uint16_t queue_id;
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};
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#define MBUF_DMA_ADDR(mb) \
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((uint64_t) ((mb)->buf_physaddr + (mb)->data_off))
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/* enforce 512B alignment on default Rx DMA addresses */
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#define MBUF_DMA_ADDR_DEFAULT(mb) \
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((uint64_t) RTE_ALIGN(((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM), 512))
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static inline void fifo_reset(struct fifo *fifo, uint32_t len)
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{
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fifo->head = fifo->tail = fifo->list;
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fifo->endp = fifo->list + len;
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}
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static inline void fifo_insert(struct fifo *fifo, uint16_t val)
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{
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*fifo->head = val;
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if (++fifo->head == fifo->endp)
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fifo->head = fifo->list;
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}
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/* do not worry about list being empty since we only check it once we know
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* we have used enough descriptors to set the RS bit at least once */
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static inline uint16_t fifo_peek(struct fifo *fifo)
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{
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return *fifo->tail;
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}
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static inline uint16_t fifo_remove(struct fifo *fifo)
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{
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uint16_t val;
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val = *fifo->tail;
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if (++fifo->tail == fifo->endp)
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fifo->tail = fifo->list;
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return val;
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}
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static inline void
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fm10k_pktmbuf_reset(struct rte_mbuf *mb, uint8_t in_port)
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{
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rte_mbuf_refcnt_set(mb, 1);
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mb->next = NULL;
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mb->nb_segs = 1;
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/* enforce 512B alignment on default Rx virtual addresses */
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mb->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb->buf_addr +
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RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
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- (char *)mb->buf_addr);
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mb->port = in_port;
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}
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/*
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* Verify Rx packet buffer alignment is valid.
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*
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* Hardware requires specific alignment for Rx packet buffers. At
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* least one of the following two conditions must be satisfied.
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* 1. Address is 512B aligned
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* 2. Address is 8B aligned and buffer does not cross 4K boundary.
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*
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* Return 1 if buffer alignment satisfies at least one condition,
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* otherwise return 0.
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*
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* Note: Alignment is checked by the driver when the Rx queue is reset. It
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* is assumed that if an entire descriptor ring can be filled with
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* buffers containing valid alignment, then all buffers in that mempool
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* have valid address alignment. It is the responsibility of the user
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* to ensure all buffers have valid alignment, as it is the user who
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* creates the mempool.
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* Note: It is assumed the buffer needs only to store a maximum size Ethernet
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* frame.
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*/
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static inline int
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fm10k_addr_alignment_valid(struct rte_mbuf *mb)
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{
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uint64_t addr = MBUF_DMA_ADDR_DEFAULT(mb);
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uint64_t boundary1, boundary2;
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/* 512B aligned? */
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if (RTE_ALIGN(addr, 512) == addr)
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return 1;
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/* 8B aligned, and max Ethernet frame would not cross a 4KB boundary? */
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if (RTE_ALIGN(addr, 8) == addr) {
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boundary1 = RTE_ALIGN_FLOOR(addr, 4096);
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boundary2 = RTE_ALIGN_FLOOR(addr + ETHER_MAX_VLAN_FRAME_LEN,
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4096);
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if (boundary1 == boundary2)
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return 1;
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}
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PMD_INIT_LOG(ERR, "Error: Invalid buffer alignment!");
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return 0;
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}
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/* Rx and Tx prototypes */
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uint16_t fm10k_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t fm10k_recv_scattered_pkts(void *rx_queue,
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struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
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uint16_t fm10k_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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#endif
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