a951c1ed3a
Hardware does not support individually enable/disable/reset the Tx or Rx
queue in hns3 network engine, driver must enable/disable/reset Tx and Rx
queues at the same time.
Currently, hns3 PMD driver does not support the scenarios as below:
1) When calling the following function, the input parameter nb_rx_q and
nb_tx_q are not equal.
rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q,
uint16_t nb_tx_q,
const struct rte_eth_conf *dev_conf);
2) When calling the following functions to setup queues, the
cumulatively setup Rx queues are not the same as the setup Tx queues.
rte_eth_rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id,,,);
rte_eth_tx_queue_setup(uint16_t port_id, uint16_t tx_queue_id,,,);
However, these are common usage scenarios in some applications, such as,
l3fwd, ip_ressmbly and OVS-DPDK, etc.
This patch adds support for this usage of these functions by setup fake
Tx or Rx queues to adjust numbers of Tx/Rx queues. But these fake queues
are imperceptible, and can not be used by upper applications.
Signed-off-by: Huisong Li <lihuisong@huawei.com>
Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
169 lines
3.8 KiB
C
169 lines
3.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018-2019 Hisilicon Limited.
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*/
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#ifndef _HNS3_DCB_H_
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#define _HNS3_DCB_H_
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/* MAC Pause */
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#define HNS3_TX_MAC_PAUSE_EN_MSK BIT(0)
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#define HNS3_RX_MAC_PAUSE_EN_MSK BIT(1)
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#define HNS3_DEFAULT_PAUSE_TRANS_GAP 0x18
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#define HNS3_DEFAULT_PAUSE_TRANS_TIME 0xFFFF
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/* SP or DWRR */
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#define HNS3_DCB_TX_SCHD_DWRR_MSK BIT(0)
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#define HNS3_DCB_TX_SCHD_SP_MSK (0xFE)
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enum hns3_shap_bucket {
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HNS3_DCB_SHAP_C_BUCKET = 0,
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HNS3_DCB_SHAP_P_BUCKET,
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};
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struct hns3_priority_weight_cmd {
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uint8_t pri_id;
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uint8_t dwrr;
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};
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struct hns3_qs_weight_cmd {
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uint16_t qs_id;
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uint8_t dwrr;
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};
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struct hns3_pg_weight_cmd {
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uint8_t pg_id;
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uint8_t dwrr;
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};
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struct hns3_ets_tc_weight_cmd {
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uint8_t tc_weight[HNS3_MAX_TC_NUM];
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uint8_t weight_offset;
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uint8_t rsvd[15];
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};
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struct hns3_qs_to_pri_link_cmd {
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uint16_t qs_id;
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uint16_t rsvd;
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uint8_t priority;
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#define HNS3_DCB_QS_PRI_LINK_VLD_MSK BIT(0)
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uint8_t link_vld;
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};
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struct hns3_nq_to_qs_link_cmd {
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uint16_t nq_id;
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uint16_t rsvd;
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#define HNS3_DCB_Q_QS_LINK_VLD_MSK BIT(10)
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uint16_t qset_id;
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};
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#define HNS3_DCB_SHAP_IR_B_MSK GENMASK(7, 0)
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#define HNS3_DCB_SHAP_IR_B_LSH 0
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#define HNS3_DCB_SHAP_IR_U_MSK GENMASK(11, 8)
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#define HNS3_DCB_SHAP_IR_U_LSH 8
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#define HNS3_DCB_SHAP_IR_S_MSK GENMASK(15, 12)
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#define HNS3_DCB_SHAP_IR_S_LSH 12
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#define HNS3_DCB_SHAP_BS_B_MSK GENMASK(20, 16)
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#define HNS3_DCB_SHAP_BS_B_LSH 16
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#define HNS3_DCB_SHAP_BS_S_MSK GENMASK(25, 21)
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#define HNS3_DCB_SHAP_BS_S_LSH 21
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struct hns3_pri_shapping_cmd {
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uint8_t pri_id;
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uint8_t rsvd[3];
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uint32_t pri_shapping_para;
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};
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struct hns3_pg_shapping_cmd {
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uint8_t pg_id;
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uint8_t rsvd[3];
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uint32_t pg_shapping_para;
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};
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#define HNS3_BP_GRP_NUM 32
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#define HNS3_BP_SUB_GRP_ID_S 0
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#define HNS3_BP_SUB_GRP_ID_M GENMASK(4, 0)
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#define HNS3_BP_GRP_ID_S 5
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#define HNS3_BP_GRP_ID_M GENMASK(9, 5)
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struct hns3_bp_to_qs_map_cmd {
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uint8_t tc_id;
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uint8_t rsvd[2];
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uint8_t qs_group_id;
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uint32_t qs_bit_map;
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uint32_t rsvd1;
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};
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struct hns3_pfc_en_cmd {
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uint8_t tx_rx_en_bitmap;
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uint8_t pri_en_bitmap;
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};
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struct hns3_port_shapping_cmd {
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uint32_t port_shapping_para;
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};
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struct hns3_cfg_pause_param_cmd {
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uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
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uint8_t pause_trans_gap;
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uint8_t rsvd;
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uint16_t pause_trans_time;
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uint8_t rsvd1[6];
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/* extra mac address to do double check for pause frame */
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uint8_t mac_addr_extra[RTE_ETHER_ADDR_LEN];
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uint16_t rsvd2;
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};
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struct hns3_pg_to_pri_link_cmd {
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uint8_t pg_id;
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uint8_t rsvd1[3];
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uint8_t pri_bit_map;
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};
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enum hns3_shaper_level {
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HNS3_SHAPER_LVL_PRI = 0,
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HNS3_SHAPER_LVL_PG = 1,
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HNS3_SHAPER_LVL_PORT = 2,
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HNS3_SHAPER_LVL_QSET = 3,
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HNS3_SHAPER_LVL_CNT = 4,
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HNS3_SHAPER_LVL_VF = 0,
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HNS3_SHAPER_LVL_PF = 1,
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};
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struct hns3_shaper_parameter {
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uint32_t ir_b; /* IR_B parameter of IR shaper */
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uint32_t ir_u; /* IR_U parameter of IR shaper */
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uint32_t ir_s; /* IR_S parameter of IR shaper */
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};
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#define hns3_dcb_set_field(dest, string, val) \
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hns3_set_field((dest), \
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(HNS3_DCB_SHAP_##string##_MSK), \
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(HNS3_DCB_SHAP_##string##_LSH), val)
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#define hns3_dcb_get_field(src, string) \
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hns3_get_field((src), (HNS3_DCB_SHAP_##string##_MSK), \
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(HNS3_DCB_SHAP_##string##_LSH))
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int hns3_pause_addr_cfg(struct hns3_hw *hw, const uint8_t *mac_addr);
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int hns3_dcb_configure(struct hns3_adapter *hns);
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int hns3_dcb_init(struct hns3_hw *hw);
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int hns3_dcb_init_hw(struct hns3_hw *hw);
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int hns3_dcb_info_init(struct hns3_hw *hw);
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int
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hns3_fc_enable(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);
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int
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hns3_dcb_pfc_enable(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf);
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void hns3_set_rss_size(struct hns3_hw *hw, uint16_t nb_rx_q);
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void hns3_tc_queue_mapping_cfg(struct hns3_hw *hw, uint16_t nb_queue);
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int hns3_dcb_cfg_update(struct hns3_adapter *hns);
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#endif /* _HNS3_DCB_H_ */
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