a0147be547
Xilinx acquired Solarflare in 2019. Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com> Acked-by: James Fox <jamesfox@xilinx.com>
176 lines
4.8 KiB
C
176 lines
4.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright(c) 2019-2020 Xilinx, Inc.
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* Copyright(c) 2018-2019 Solarflare Communications Inc.
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*
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* This software was jointly developed between OKTET Labs (under contract
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* for Solarflare) and Solarflare Communications, Inc.
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*/
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#ifndef _SFC_EF10_RX_EV_H
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#define _SFC_EF10_RX_EV_H
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#include <rte_mbuf.h>
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#include "efx_types.h"
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#include "efx_regs.h"
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#include "efx_regs_ef10.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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static inline void
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sfc_ef10_rx_ev_to_offloads(const efx_qword_t rx_ev, struct rte_mbuf *m,
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uint64_t ol_mask)
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{
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uint32_t tun_ptype = 0;
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/* Which event bit is mapped to PKT_RX_IP_CKSUM_* */
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int8_t ip_csum_err_bit;
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/* Which event bit is mapped to PKT_RX_L4_CKSUM_* */
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int8_t l4_csum_err_bit;
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uint32_t l2_ptype = 0;
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uint32_t l3_ptype = 0;
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uint32_t l4_ptype = 0;
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uint64_t ol_flags = 0;
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if (unlikely(rx_ev.eq_u64[0] &
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rte_cpu_to_le_64((1ull << ESF_DZ_RX_ECC_ERR_LBN) |
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(1ull << ESF_DZ_RX_ECRC_ERR_LBN) |
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(1ull << ESF_DZ_RX_PARSE_INCOMPLETE_LBN)))) {
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/* Zero packet type is used as a marker to dicard bad packets */
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goto done;
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}
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#if SFC_EF10_RX_EV_ENCAP_SUPPORT
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switch (EFX_QWORD_FIELD(rx_ev, ESF_EZ_RX_ENCAP_HDR)) {
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default:
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/* Unexpected encapsulation tag class */
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SFC_ASSERT(false);
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/* FALLTHROUGH */
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case ESE_EZ_ENCAP_HDR_NONE:
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break;
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case ESE_EZ_ENCAP_HDR_VXLAN:
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/*
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* It is definitely UDP, but we have no information
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* about IPv4 vs IPv6 and VLAN tagging.
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*/
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tun_ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP;
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break;
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case ESE_EZ_ENCAP_HDR_GRE:
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/*
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* We have no information about IPv4 vs IPv6 and VLAN tagging.
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*/
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tun_ptype = RTE_PTYPE_TUNNEL_NVGRE;
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break;
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}
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#endif
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if (tun_ptype == 0) {
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ip_csum_err_bit = ESF_DZ_RX_IPCKSUM_ERR_LBN;
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l4_csum_err_bit = ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN;
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} else {
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ip_csum_err_bit = ESF_EZ_RX_IP_INNER_CHKSUM_ERR_LBN;
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l4_csum_err_bit = ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_LBN;
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if (unlikely(EFX_TEST_QWORD_BIT(rx_ev,
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ESF_DZ_RX_IPCKSUM_ERR_LBN)))
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ol_flags |= PKT_RX_EIP_CKSUM_BAD;
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}
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switch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_ETH_TAG_CLASS)) {
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case ESE_DZ_ETH_TAG_CLASS_NONE:
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l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER :
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RTE_PTYPE_INNER_L2_ETHER;
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break;
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case ESE_DZ_ETH_TAG_CLASS_VLAN1:
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l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER_VLAN :
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RTE_PTYPE_INNER_L2_ETHER_VLAN;
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break;
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case ESE_DZ_ETH_TAG_CLASS_VLAN2:
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l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER_QINQ :
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RTE_PTYPE_INNER_L2_ETHER_QINQ;
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break;
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default:
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/* Unexpected Eth tag class */
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SFC_ASSERT(false);
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}
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switch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_L3_CLASS)) {
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case ESE_DZ_L3_CLASS_IP4_FRAG:
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l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_FRAG :
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RTE_PTYPE_INNER_L4_FRAG;
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/* FALLTHROUGH */
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case ESE_DZ_L3_CLASS_IP4:
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l3_ptype = (tun_ptype == 0) ? RTE_PTYPE_L3_IPV4_EXT_UNKNOWN :
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RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
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ol_flags |= PKT_RX_RSS_HASH |
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((EFX_TEST_QWORD_BIT(rx_ev, ip_csum_err_bit)) ?
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PKT_RX_IP_CKSUM_BAD : PKT_RX_IP_CKSUM_GOOD);
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break;
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case ESE_DZ_L3_CLASS_IP6_FRAG:
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l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_FRAG :
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RTE_PTYPE_INNER_L4_FRAG;
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/* FALLTHROUGH */
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case ESE_DZ_L3_CLASS_IP6:
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l3_ptype = (tun_ptype == 0) ? RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
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RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
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ol_flags |= PKT_RX_RSS_HASH;
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break;
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case ESE_DZ_L3_CLASS_ARP:
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/* Override Layer 2 packet type */
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/* There is no ARP classification for inner packets */
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if (tun_ptype == 0)
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l2_ptype = RTE_PTYPE_L2_ETHER_ARP;
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break;
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case ESE_DZ_L3_CLASS_UNKNOWN:
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break;
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default:
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/* Unexpected Layer 3 class */
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SFC_ASSERT(false);
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}
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/*
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* RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is only
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* 2 bits wide on Medford2. Check it is safe to use the Medford2 field
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* and values for all EF10 controllers.
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*/
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RTE_BUILD_BUG_ON(ESF_FZ_RX_L4_CLASS_LBN != ESF_DE_RX_L4_CLASS_LBN);
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switch (EFX_QWORD_FIELD(rx_ev, ESF_FZ_RX_L4_CLASS)) {
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case ESE_FZ_L4_CLASS_TCP:
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RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_TCP != ESE_DE_L4_CLASS_TCP);
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l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_TCP :
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RTE_PTYPE_INNER_L4_TCP;
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ol_flags |=
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(EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ?
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PKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD;
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break;
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case ESE_FZ_L4_CLASS_UDP:
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RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_UDP != ESE_DE_L4_CLASS_UDP);
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l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_UDP :
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RTE_PTYPE_INNER_L4_UDP;
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ol_flags |=
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(EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ?
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PKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD;
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break;
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case ESE_FZ_L4_CLASS_UNKNOWN:
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RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_UNKNOWN !=
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ESE_DE_L4_CLASS_UNKNOWN);
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break;
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default:
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/* Unexpected Layer 4 class */
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SFC_ASSERT(false);
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}
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SFC_ASSERT(l2_ptype != 0);
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done:
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m->ol_flags = ol_flags & ol_mask;
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m->packet_type = tun_ptype | l2_ptype | l3_ptype | l4_ptype;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SFC_EF10_RX_EV_H */
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