97d37d2c1f
UAR (User Access Region) register does not need to be remapped for primary process but it should be remapped only for secondary process. UAR register table is in the process private structure in rte_eth_devices[], (struct mlx4_proc_priv *)rte_eth_devices[port_id].process_private The actual UAR table follows the data structure and the table is used for both Tx and Rx. For Tx, BlueFlame in UAR is used to ring the doorbell. MLX4_TX_BFREG(txq) is defined to get a register for the txq. Processes access its own private data to acquire the register from the UAR table. For Rx, the doorbell in UAR is required in arming CQ event. However, it is a known issue that the register isn't remapped for secondary process. Signed-off-by: Yongseok Koh <yskoh@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
164 lines
4.6 KiB
C
164 lines
4.6 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2017 6WIND S.A.
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* Copyright 2017 Mellanox Technologies, Ltd
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*/
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#ifndef MLX4_PRM_H_
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#define MLX4_PRM_H_
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#include <rte_atomic.h>
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#include <rte_branch_prediction.h>
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#include <rte_byteorder.h>
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/* Verbs headers do not support -pedantic. */
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#ifdef PEDANTIC
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#pragma GCC diagnostic ignored "-Wpedantic"
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#endif
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#include <infiniband/mlx4dv.h>
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#include <infiniband/verbs.h>
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#ifdef PEDANTIC
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#pragma GCC diagnostic error "-Wpedantic"
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#endif
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#include "mlx4_autoconf.h"
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/* ConnectX-3 Tx queue basic block. */
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#define MLX4_TXBB_SHIFT 6
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#define MLX4_TXBB_SIZE (1 << MLX4_TXBB_SHIFT)
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/* Typical TSO descriptor with 16 gather entries is 352 bytes. */
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#define MLX4_MAX_SGE 32
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#define MLX4_MAX_WQE_SIZE \
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(MLX4_MAX_SGE * sizeof(struct mlx4_wqe_data_seg) + \
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sizeof(struct mlx4_wqe_ctrl_seg))
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#define MLX4_SEG_SHIFT 4
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/* Send queue stamping/invalidating information. */
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#define MLX4_SQ_STAMP_STRIDE 64
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#define MLX4_SQ_STAMP_DWORDS (MLX4_SQ_STAMP_STRIDE / 4)
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#define MLX4_SQ_OWNER_BIT 31
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#define MLX4_SQ_STAMP_VAL 0x7fffffff
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/* Work queue element (WQE) flags. */
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#define MLX4_WQE_CTRL_IIP_HDR_CSUM (1 << 28)
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#define MLX4_WQE_CTRL_IL4_HDR_CSUM (1 << 27)
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#define MLX4_WQE_CTRL_RR (1 << 6)
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/* CQE checksum flags. */
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enum {
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MLX4_CQE_L2_TUNNEL_IPV4 = (int)(1u << 25),
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MLX4_CQE_L2_TUNNEL_L4_CSUM = (int)(1u << 26),
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MLX4_CQE_L2_TUNNEL = (int)(1u << 27),
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MLX4_CQE_L2_VLAN_MASK = (int)(3u << 29),
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MLX4_CQE_L2_TUNNEL_IPOK = (int)(1u << 31),
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};
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/* CQE status flags. */
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#define MLX4_CQE_STATUS_IPV6F (1 << 12)
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#define MLX4_CQE_STATUS_IPV4 (1 << 22)
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#define MLX4_CQE_STATUS_IPV4F (1 << 23)
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#define MLX4_CQE_STATUS_IPV6 (1 << 24)
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#define MLX4_CQE_STATUS_IPV4OPT (1 << 25)
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#define MLX4_CQE_STATUS_TCP (1 << 26)
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#define MLX4_CQE_STATUS_UDP (1 << 27)
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#define MLX4_CQE_STATUS_PTYPE_MASK \
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(MLX4_CQE_STATUS_IPV4 | \
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MLX4_CQE_STATUS_IPV4F | \
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MLX4_CQE_STATUS_IPV6 | \
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MLX4_CQE_STATUS_IPV4OPT | \
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MLX4_CQE_STATUS_TCP | \
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MLX4_CQE_STATUS_UDP)
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/* Send queue information. */
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struct mlx4_sq {
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volatile uint8_t *buf; /**< SQ buffer. */
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volatile uint8_t *eob; /**< End of SQ buffer */
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uint32_t size; /**< SQ size includes headroom. */
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uint32_t remain_size; /**< Remaining WQE room in SQ (bytes). */
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uint32_t owner_opcode;
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/**< Default owner opcode with HW valid owner bit. */
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uint32_t stamp; /**< Stamp value with an invalid HW owner bit. */
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uint32_t *db; /**< Pointer to the doorbell. */
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off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
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uint32_t doorbell_qpn; /**< qp number to write to the doorbell. */
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};
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/* Completion queue events, numbers and masks. */
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#define MLX4_CQ_DB_GEQ_N_MASK 0x3
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#define MLX4_CQ_DOORBELL 0x20
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#define MLX4_CQ_DB_CI_MASK 0xffffff
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/* Completion queue information. */
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struct mlx4_cq {
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volatile void *cq_uar; /**< CQ user access region. */
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volatile void *cq_db_reg; /**< CQ doorbell register. */
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volatile uint32_t *set_ci_db; /**< Pointer to the CQ doorbell. */
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volatile uint32_t *arm_db; /**< Arming Rx events doorbell. */
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volatile uint8_t *buf; /**< Pointer to the completion queue buffer. */
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uint32_t cqe_cnt; /**< Number of entries in the queue. */
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uint32_t cqe_64:1; /**< CQ entry size is 64 bytes. */
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uint32_t cons_index; /**< Last queue entry that was handled. */
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uint32_t cqn; /**< CQ number. */
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int arm_sn; /**< Rx event counter. */
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};
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#ifndef HAVE_IBV_MLX4_WQE_LSO_SEG
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/*
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* WQE LSO segment structure.
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* Defined here as backward compatibility for rdma-core v17 and below.
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* Similar definition is found in infiniband/mlx4dv.h in rdma-core v18
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* and above.
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*/
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struct mlx4_wqe_lso_seg {
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rte_be32_t mss_hdr_size;
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rte_be32_t header[];
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};
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#endif
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/**
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* Retrieve a CQE entry from a CQ.
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*
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* cqe = cq->buf + cons_index * cqe_size + cqe_offset
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*
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* Where cqe_size is 32 or 64 bytes and cqe_offset is 0 or 32 (depending on
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* cqe_size).
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*
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* @param cq
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* CQ to retrieve entry from.
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* @param index
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* Entry index.
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*
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* @return
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* Pointer to CQE entry.
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*/
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static inline volatile struct mlx4_cqe *
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mlx4_get_cqe(struct mlx4_cq *cq, uint32_t index)
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{
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return (volatile struct mlx4_cqe *)(cq->buf +
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((index & (cq->cqe_cnt - 1)) <<
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(5 + cq->cqe_64)) +
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(cq->cqe_64 << 5));
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}
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/**
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* Transpose a flag in a value.
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*
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* @param val
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* Input value.
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* @param from
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* Flag to retrieve from input value.
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* @param to
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* Flag to set in output value.
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*
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* @return
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* Output value with transposed flag enabled if present on input.
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*/
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static inline uint64_t
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mlx4_transpose(uint64_t val, uint64_t from, uint64_t to)
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{
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return (from >= to ?
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(val & from) / (from / to) :
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(val & from) * (to / from));
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}
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#endif /* MLX4_PRM_H_ */
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