d9f0d3a1ff
Users compiling DPDK should not need to know or care about the arrangement of cachelines in the rte_ring structure. Therefore just remove the build option and set the structures to be always split. On platforms with 64B cachelines, for improved performance use 128B rather than 64B alignment since it stops the producer and consumer data being on adjacent cachelines. Signed-off-by: Bruce Richardson <bruce.richardson@intel.com> Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Acked-by: Olivier Matz <olivier.matz@6wind.com> |
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