d27fb0de2f
Bit-fields in mlx5_rxq_data can be changed on the fly by a control plane - e.g. rxq->mark. However, vectorized Rx uses a bit-field to mark pending errors. Even if one bit is written, consequence is to write the whole integer and this can cause a synchronization issue - two entities write to a same block without locking. As the pending_err bit is entirely internal use for the datapath, this can be replaced with a local variable. Fixes:6cb559d67b("net/mlx5: add vectorized Rx/Tx burst for x86") Fixes:570acdb1da("net/mlx5: add vectorized Rx/Tx burst for ARM") Cc: stable@dpdk.org Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
706 lines
22 KiB
C
706 lines
22 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright 2015 6WIND S.A.
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* Copyright 2015 Mellanox.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of 6WIND S.A. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef RTE_PMD_MLX5_RXTX_H_
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#define RTE_PMD_MLX5_RXTX_H_
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#include <stddef.h>
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#include <stdint.h>
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#include <sys/queue.h>
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/* Verbs header. */
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/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
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#ifdef PEDANTIC
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#pragma GCC diagnostic ignored "-Wpedantic"
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#endif
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#include <infiniband/verbs.h>
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#include <infiniband/mlx5dv.h>
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#ifdef PEDANTIC
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#pragma GCC diagnostic error "-Wpedantic"
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#endif
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#include <rte_mbuf.h>
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#include <rte_mempool.h>
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#include <rte_common.h>
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#include <rte_hexdump.h>
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#include <rte_atomic.h>
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#include "mlx5_utils.h"
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#include "mlx5.h"
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#include "mlx5_autoconf.h"
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#include "mlx5_defs.h"
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#include "mlx5_prm.h"
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struct mlx5_rxq_stats {
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unsigned int idx; /**< Mapping index. */
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#ifdef MLX5_PMD_SOFT_COUNTERS
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uint64_t ipackets; /**< Total of successfully received packets. */
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uint64_t ibytes; /**< Total of successfully received bytes. */
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#endif
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uint64_t idropped; /**< Total of packets dropped when RX ring full. */
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uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
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};
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struct mlx5_txq_stats {
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unsigned int idx; /**< Mapping index. */
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#ifdef MLX5_PMD_SOFT_COUNTERS
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uint64_t opackets; /**< Total of successfully sent packets. */
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uint64_t obytes; /**< Total of successfully sent bytes. */
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#endif
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uint64_t oerrors; /**< Total number of failed transmitted packets. */
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};
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struct priv;
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/* Memory region queue object. */
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struct mlx5_mr {
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LIST_ENTRY(mlx5_mr) next; /**< Pointer to the next element. */
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rte_atomic32_t refcnt; /*<< Reference counter. */
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uint32_t lkey; /*<< rte_cpu_to_be_32(mr->lkey) */
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uintptr_t start; /* Start address of MR */
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uintptr_t end; /* End address of MR */
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struct ibv_mr *mr; /*<< Memory Region. */
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struct rte_mempool *mp; /*<< Memory Pool. */
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};
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/* Compressed CQE context. */
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struct rxq_zip {
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uint16_t ai; /* Array index. */
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uint16_t ca; /* Current array index. */
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uint16_t na; /* Next array index. */
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uint16_t cq_ci; /* The next CQE. */
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uint32_t cqe_cnt; /* Number of CQEs. */
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};
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/* RX queue descriptor. */
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struct mlx5_rxq_data {
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unsigned int csum:1; /* Enable checksum offloading. */
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unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
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unsigned int hw_timestamp:1; /* Enable HW timestamp. */
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unsigned int vlan_strip:1; /* Enable VLAN stripping. */
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unsigned int crc_present:1; /* CRC must be subtracted. */
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unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
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unsigned int cqe_n:4; /* Log 2 of CQ elements. */
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unsigned int elts_n:4; /* Log 2 of Mbufs. */
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unsigned int rss_hash:1; /* RSS hash result is enabled. */
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unsigned int mark:1; /* Marked flow available on the queue. */
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unsigned int :15; /* Remaining bits. */
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volatile uint32_t *rq_db;
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volatile uint32_t *cq_db;
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uint16_t port_id;
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uint16_t rq_ci;
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uint16_t rq_pi;
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uint16_t cq_ci;
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volatile struct mlx5_wqe_data_seg(*wqes)[];
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volatile struct mlx5_cqe(*cqes)[];
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struct rxq_zip zip; /* Compressed context. */
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struct rte_mbuf *(*elts)[];
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struct rte_mempool *mp;
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struct mlx5_rxq_stats stats;
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uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
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struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
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void *cq_uar; /* CQ user access region. */
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uint32_t cqn; /* CQ number. */
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uint8_t cq_arm_sn; /* CQ arm seq number. */
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} __rte_cache_aligned;
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/* Verbs Rx queue elements. */
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struct mlx5_rxq_ibv {
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LIST_ENTRY(mlx5_rxq_ibv) next; /* Pointer to the next element. */
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rte_atomic32_t refcnt; /* Reference counter. */
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struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
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struct ibv_cq *cq; /* Completion Queue. */
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struct ibv_wq *wq; /* Work Queue. */
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struct ibv_comp_channel *channel;
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struct mlx5_mr *mr; /* Memory Region (for mp). */
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};
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/* RX queue control descriptor. */
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struct mlx5_rxq_ctrl {
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LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
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rte_atomic32_t refcnt; /* Reference counter. */
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struct priv *priv; /* Back pointer to private data. */
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struct mlx5_rxq_ibv *ibv; /* Verbs elements. */
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struct mlx5_rxq_data rxq; /* Data path structure. */
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unsigned int socket; /* CPU socket ID for allocations. */
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unsigned int irq:1; /* Whether IRQ is enabled. */
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};
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/* Indirection table. */
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struct mlx5_ind_table_ibv {
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LIST_ENTRY(mlx5_ind_table_ibv) next; /* Pointer to the next element. */
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rte_atomic32_t refcnt; /* Reference counter. */
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struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
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uint16_t queues_n; /**< Number of queues in the list. */
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uint16_t queues[]; /**< Queue list. */
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};
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/* Hash Rx queue. */
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struct mlx5_hrxq {
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LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
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rte_atomic32_t refcnt; /* Reference counter. */
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struct mlx5_ind_table_ibv *ind_table; /* Indirection table. */
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struct ibv_qp *qp; /* Verbs queue pair. */
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uint64_t hash_fields; /* Verbs Hash fields. */
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uint8_t rss_key_len; /* Hash key length in bytes. */
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uint8_t rss_key[]; /* Hash key. */
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};
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/* TX queue descriptor. */
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__extension__
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struct mlx5_txq_data {
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uint16_t elts_head; /* Current counter in (*elts)[]. */
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uint16_t elts_tail; /* Counter of first element awaiting completion. */
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uint16_t elts_comp; /* Counter since last completion request. */
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uint16_t mpw_comp; /* WQ index since last completion request. */
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uint16_t cq_ci; /* Consumer index for completion queue. */
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#ifndef NDEBUG
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uint16_t cq_pi; /* Producer index for completion queue. */
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#endif
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uint16_t wqe_ci; /* Consumer index for work queue. */
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uint16_t wqe_pi; /* Producer index for work queue. */
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uint16_t elts_n:4; /* (*elts)[] length (in log2). */
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uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
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uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
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uint16_t tso_en:1; /* When set hardware TSO is enabled. */
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uint16_t tunnel_en:1;
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/* When set TX offload for tunneled packets are supported. */
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uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
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uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
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uint16_t inline_max_packet_sz; /* Max packet size for inlining. */
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uint16_t mr_cache_idx; /* Index of last hit entry. */
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uint32_t qp_num_8s; /* QP number shifted by 8. */
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uint32_t flags; /* Flags for Tx Queue. */
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volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
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volatile void *wqes; /* Work queue (use volatile to write into). */
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volatile uint32_t *qp_db; /* Work queue doorbell. */
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volatile uint32_t *cq_db; /* Completion queue doorbell. */
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volatile void *bf_reg; /* Blueflame register. */
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struct mlx5_mr *mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MR translation table. */
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struct rte_mbuf *(*elts)[]; /* TX elements. */
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struct mlx5_txq_stats stats; /* TX queue counters. */
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} __rte_cache_aligned;
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/* Verbs Rx queue elements. */
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struct mlx5_txq_ibv {
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LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */
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rte_atomic32_t refcnt; /* Reference counter. */
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struct ibv_cq *cq; /* Completion Queue. */
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struct ibv_qp *qp; /* Queue Pair. */
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};
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/* TX queue control descriptor. */
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struct mlx5_txq_ctrl {
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LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
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rte_atomic32_t refcnt; /* Reference counter. */
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struct priv *priv; /* Back pointer to private data. */
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unsigned int socket; /* CPU socket ID for allocations. */
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unsigned int max_inline_data; /* Max inline data. */
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unsigned int max_tso_header; /* Max TSO header size. */
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struct mlx5_txq_ibv *ibv; /* Verbs queue object. */
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struct mlx5_txq_data txq; /* Data path structure. */
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off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
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};
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/* mlx5_rxq.c */
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extern uint8_t rss_hash_default_key[];
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extern const size_t rss_hash_default_key_len;
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void mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *);
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int mlx5_rx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
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const struct rte_eth_rxconf *, struct rte_mempool *);
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void mlx5_rx_queue_release(void *);
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int priv_rx_intr_vec_enable(struct priv *priv);
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void priv_rx_intr_vec_disable(struct priv *priv);
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int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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struct mlx5_rxq_ibv *mlx5_priv_rxq_ibv_new(struct priv *, uint16_t);
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struct mlx5_rxq_ibv *mlx5_priv_rxq_ibv_get(struct priv *, uint16_t);
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int mlx5_priv_rxq_ibv_release(struct priv *, struct mlx5_rxq_ibv *);
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int mlx5_priv_rxq_ibv_releasable(struct priv *, struct mlx5_rxq_ibv *);
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int mlx5_priv_rxq_ibv_verify(struct priv *);
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struct mlx5_rxq_ctrl *mlx5_priv_rxq_new(struct priv *, uint16_t,
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uint16_t, unsigned int,
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struct rte_mempool *);
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struct mlx5_rxq_ctrl *mlx5_priv_rxq_get(struct priv *, uint16_t);
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int mlx5_priv_rxq_release(struct priv *, uint16_t);
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int mlx5_priv_rxq_releasable(struct priv *, uint16_t);
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int mlx5_priv_rxq_verify(struct priv *);
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int rxq_alloc_elts(struct mlx5_rxq_ctrl *);
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struct mlx5_ind_table_ibv *mlx5_priv_ind_table_ibv_new(struct priv *,
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uint16_t [],
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uint16_t);
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struct mlx5_ind_table_ibv *mlx5_priv_ind_table_ibv_get(struct priv *,
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uint16_t [],
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uint16_t);
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int mlx5_priv_ind_table_ibv_release(struct priv *, struct mlx5_ind_table_ibv *);
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int mlx5_priv_ind_table_ibv_verify(struct priv *);
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struct mlx5_hrxq *mlx5_priv_hrxq_new(struct priv *, uint8_t *, uint8_t,
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uint64_t, uint16_t [], uint16_t);
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struct mlx5_hrxq *mlx5_priv_hrxq_get(struct priv *, uint8_t *, uint8_t,
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uint64_t, uint16_t [], uint16_t);
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int mlx5_priv_hrxq_release(struct priv *, struct mlx5_hrxq *);
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int mlx5_priv_hrxq_ibv_verify(struct priv *);
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/* mlx5_txq.c */
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int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
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const struct rte_eth_txconf *);
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void mlx5_tx_queue_release(void *);
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int priv_tx_uar_remap(struct priv *priv, int fd);
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struct mlx5_txq_ibv *mlx5_priv_txq_ibv_new(struct priv *, uint16_t);
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struct mlx5_txq_ibv *mlx5_priv_txq_ibv_get(struct priv *, uint16_t);
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int mlx5_priv_txq_ibv_release(struct priv *, struct mlx5_txq_ibv *);
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int mlx5_priv_txq_ibv_releasable(struct priv *, struct mlx5_txq_ibv *);
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int mlx5_priv_txq_ibv_verify(struct priv *);
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struct mlx5_txq_ctrl *mlx5_priv_txq_new(struct priv *, uint16_t,
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uint16_t, unsigned int,
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const struct rte_eth_txconf *);
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struct mlx5_txq_ctrl *mlx5_priv_txq_get(struct priv *, uint16_t);
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int mlx5_priv_txq_release(struct priv *, uint16_t);
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int mlx5_priv_txq_releasable(struct priv *, uint16_t);
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int mlx5_priv_txq_verify(struct priv *);
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void txq_alloc_elts(struct mlx5_txq_ctrl *);
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/* mlx5_rxtx.c */
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extern uint32_t mlx5_ptype_table[];
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void mlx5_set_ptype_table(void);
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uint16_t mlx5_tx_burst(void *, struct rte_mbuf **, uint16_t);
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uint16_t mlx5_tx_burst_mpw(void *, struct rte_mbuf **, uint16_t);
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uint16_t mlx5_tx_burst_mpw_inline(void *, struct rte_mbuf **, uint16_t);
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uint16_t mlx5_tx_burst_empw(void *, struct rte_mbuf **, uint16_t);
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uint16_t mlx5_rx_burst(void *, struct rte_mbuf **, uint16_t);
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uint16_t removed_tx_burst(void *, struct rte_mbuf **, uint16_t);
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uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t);
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int mlx5_rx_descriptor_status(void *, uint16_t);
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int mlx5_tx_descriptor_status(void *, uint16_t);
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/* Vectorized version of mlx5_rxtx.c */
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int priv_check_raw_vec_tx_support(struct priv *);
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int priv_check_vec_tx_support(struct priv *);
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int rxq_check_vec_support(struct mlx5_rxq_data *);
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int priv_check_vec_rx_support(struct priv *);
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uint16_t mlx5_tx_burst_raw_vec(void *, struct rte_mbuf **, uint16_t);
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uint16_t mlx5_tx_burst_vec(void *, struct rte_mbuf **, uint16_t);
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uint16_t mlx5_rx_burst_vec(void *, struct rte_mbuf **, uint16_t);
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/* mlx5_mr.c */
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void mlx5_mp2mr_iter(struct rte_mempool *, void *);
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struct mlx5_mr *priv_txq_mp2mr_reg(struct priv *priv, struct mlx5_txq_data *,
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struct rte_mempool *, unsigned int);
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struct mlx5_mr *mlx5_txq_mp2mr_reg(struct mlx5_txq_data *, struct rte_mempool *,
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unsigned int);
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#ifndef NDEBUG
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/**
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* Verify or set magic value in CQE.
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*
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* @param cqe
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* Pointer to CQE.
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*
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* @return
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* 0 the first time.
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*/
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static inline int
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check_cqe_seen(volatile struct mlx5_cqe *cqe)
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{
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static const uint8_t magic[] = "seen";
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volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
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int ret = 1;
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unsigned int i;
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for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
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if (!ret || (*buf)[i] != magic[i]) {
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ret = 0;
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(*buf)[i] = magic[i];
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}
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return ret;
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}
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#endif /* NDEBUG */
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/**
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* Check whether CQE is valid.
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*
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* @param cqe
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* Pointer to CQE.
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* @param cqes_n
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* Size of completion queue.
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* @param ci
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* Consumer index.
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*
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* @return
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* 0 on success, 1 on failure.
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*/
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static __rte_always_inline int
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check_cqe(volatile struct mlx5_cqe *cqe,
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unsigned int cqes_n, const uint16_t ci)
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{
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uint16_t idx = ci & cqes_n;
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uint8_t op_own = cqe->op_own;
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uint8_t op_owner = MLX5_CQE_OWNER(op_own);
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uint8_t op_code = MLX5_CQE_OPCODE(op_own);
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if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
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return 1; /* No CQE. */
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#ifndef NDEBUG
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if ((op_code == MLX5_CQE_RESP_ERR) ||
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(op_code == MLX5_CQE_REQ_ERR)) {
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volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
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uint8_t syndrome = err_cqe->syndrome;
|
|
|
|
if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
|
|
(syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
|
|
return 0;
|
|
if (!check_cqe_seen(cqe)) {
|
|
ERROR("unexpected CQE error %u (0x%02x)"
|
|
" syndrome 0x%02x",
|
|
op_code, op_code, syndrome);
|
|
rte_hexdump(stderr, "MLX5 Error CQE:",
|
|
(const void *)((uintptr_t)err_cqe),
|
|
sizeof(*err_cqe));
|
|
}
|
|
return 1;
|
|
} else if ((op_code != MLX5_CQE_RESP_SEND) &&
|
|
(op_code != MLX5_CQE_REQ)) {
|
|
if (!check_cqe_seen(cqe)) {
|
|
ERROR("unexpected CQE opcode %u (0x%02x)",
|
|
op_code, op_code);
|
|
rte_hexdump(stderr, "MLX5 CQE:",
|
|
(const void *)((uintptr_t)cqe),
|
|
sizeof(*cqe));
|
|
}
|
|
return 1;
|
|
}
|
|
#endif /* NDEBUG */
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* Return the address of the WQE.
|
|
*
|
|
* @param txq
|
|
* Pointer to TX queue structure.
|
|
* @param wqe_ci
|
|
* WQE consumer index.
|
|
*
|
|
* @return
|
|
* WQE address.
|
|
*/
|
|
static inline uintptr_t *
|
|
tx_mlx5_wqe(struct mlx5_txq_data *txq, uint16_t ci)
|
|
{
|
|
ci &= ((1 << txq->wqe_n) - 1);
|
|
return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
|
|
}
|
|
|
|
/**
|
|
* Manage TX completions.
|
|
*
|
|
* When sending a burst, mlx5_tx_burst() posts several WRs.
|
|
*
|
|
* @param txq
|
|
* Pointer to TX queue structure.
|
|
*/
|
|
static __rte_always_inline void
|
|
mlx5_tx_complete(struct mlx5_txq_data *txq)
|
|
{
|
|
const uint16_t elts_n = 1 << txq->elts_n;
|
|
const uint16_t elts_m = elts_n - 1;
|
|
const unsigned int cqe_n = 1 << txq->cqe_n;
|
|
const unsigned int cqe_cnt = cqe_n - 1;
|
|
uint16_t elts_free = txq->elts_tail;
|
|
uint16_t elts_tail;
|
|
uint16_t cq_ci = txq->cq_ci;
|
|
volatile struct mlx5_cqe *cqe = NULL;
|
|
volatile struct mlx5_wqe_ctrl *ctrl;
|
|
struct rte_mbuf *m, *free[elts_n];
|
|
struct rte_mempool *pool = NULL;
|
|
unsigned int blk_n = 0;
|
|
|
|
cqe = &(*txq->cqes)[cq_ci & cqe_cnt];
|
|
if (unlikely(check_cqe(cqe, cqe_n, cq_ci)))
|
|
return;
|
|
#ifndef NDEBUG
|
|
if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
|
|
(MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
|
|
if (!check_cqe_seen(cqe)) {
|
|
ERROR("unexpected error CQE, TX stopped");
|
|
rte_hexdump(stderr, "MLX5 TXQ:",
|
|
(const void *)((uintptr_t)txq->wqes),
|
|
((1 << txq->wqe_n) *
|
|
MLX5_WQE_SIZE));
|
|
}
|
|
return;
|
|
}
|
|
#endif /* NDEBUG */
|
|
++cq_ci;
|
|
txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter);
|
|
ctrl = (volatile struct mlx5_wqe_ctrl *)
|
|
tx_mlx5_wqe(txq, txq->wqe_pi);
|
|
elts_tail = ctrl->ctrl3;
|
|
assert((elts_tail & elts_m) < (1 << txq->wqe_n));
|
|
/* Free buffers. */
|
|
while (elts_free != elts_tail) {
|
|
m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]);
|
|
if (likely(m != NULL)) {
|
|
if (likely(m->pool == pool)) {
|
|
free[blk_n++] = m;
|
|
} else {
|
|
if (likely(pool != NULL))
|
|
rte_mempool_put_bulk(pool,
|
|
(void *)free,
|
|
blk_n);
|
|
free[0] = m;
|
|
pool = m->pool;
|
|
blk_n = 1;
|
|
}
|
|
}
|
|
}
|
|
if (blk_n)
|
|
rte_mempool_put_bulk(pool, (void *)free, blk_n);
|
|
#ifndef NDEBUG
|
|
elts_free = txq->elts_tail;
|
|
/* Poisoning. */
|
|
while (elts_free != elts_tail) {
|
|
memset(&(*txq->elts)[elts_free & elts_m],
|
|
0x66,
|
|
sizeof((*txq->elts)[elts_free & elts_m]));
|
|
++elts_free;
|
|
}
|
|
#endif
|
|
txq->cq_ci = cq_ci;
|
|
txq->elts_tail = elts_tail;
|
|
/* Update the consumer index. */
|
|
rte_compiler_barrier();
|
|
*txq->cq_db = rte_cpu_to_be_32(cq_ci);
|
|
}
|
|
|
|
/**
|
|
* Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
|
|
* the cloned mbuf is allocated is returned instead.
|
|
*
|
|
* @param buf
|
|
* Pointer to mbuf.
|
|
*
|
|
* @return
|
|
* Memory pool where data is located for given mbuf.
|
|
*/
|
|
static struct rte_mempool *
|
|
mlx5_tx_mb2mp(struct rte_mbuf *buf)
|
|
{
|
|
if (unlikely(RTE_MBUF_INDIRECT(buf)))
|
|
return rte_mbuf_from_indirect(buf)->pool;
|
|
return buf->pool;
|
|
}
|
|
|
|
/**
|
|
* Get Memory Region (MR) <-> rte_mbuf association from txq->mp2mr[].
|
|
* Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
|
|
* remove an entry first.
|
|
*
|
|
* @param txq
|
|
* Pointer to TX queue structure.
|
|
* @param[in] mp
|
|
* Memory Pool for which a Memory Region lkey must be returned.
|
|
*
|
|
* @return
|
|
* mr->lkey on success, (uint32_t)-1 on failure.
|
|
*/
|
|
static __rte_always_inline uint32_t
|
|
mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
|
|
{
|
|
uint16_t i = txq->mr_cache_idx;
|
|
uintptr_t addr = rte_pktmbuf_mtod_offset(mb, uintptr_t, DATA_LEN(mb));
|
|
struct mlx5_mr *mr;
|
|
|
|
assert(i < RTE_DIM(txq->mp2mr));
|
|
if (likely(txq->mp2mr[i]->start <= addr && txq->mp2mr[i]->end >= addr))
|
|
return txq->mp2mr[i]->lkey;
|
|
for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
|
|
if (unlikely(txq->mp2mr[i]->mr == NULL)) {
|
|
/* Unknown MP, add a new MR for it. */
|
|
break;
|
|
}
|
|
if (txq->mp2mr[i]->start <= addr &&
|
|
txq->mp2mr[i]->end >= addr) {
|
|
assert(txq->mp2mr[i]->lkey != (uint32_t)-1);
|
|
assert(rte_cpu_to_be_32(txq->mp2mr[i]->mr->lkey) ==
|
|
txq->mp2mr[i]->lkey);
|
|
txq->mr_cache_idx = i;
|
|
return txq->mp2mr[i]->lkey;
|
|
}
|
|
}
|
|
txq->mr_cache_idx = 0;
|
|
mr = mlx5_txq_mp2mr_reg(txq, mlx5_tx_mb2mp(mb), i);
|
|
/*
|
|
* Request the reference to use in this queue, the original one is
|
|
* kept by the control plane.
|
|
*/
|
|
if (mr) {
|
|
rte_atomic32_inc(&mr->refcnt);
|
|
return mr->lkey;
|
|
}
|
|
return (uint32_t)-1;
|
|
}
|
|
|
|
/**
|
|
* Ring TX queue doorbell and flush the update if requested.
|
|
*
|
|
* @param txq
|
|
* Pointer to TX queue structure.
|
|
* @param wqe
|
|
* Pointer to the last WQE posted in the NIC.
|
|
* @param cond
|
|
* Request for write memory barrier after BlueFlame update.
|
|
*/
|
|
static __rte_always_inline void
|
|
mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
|
|
int cond)
|
|
{
|
|
uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
|
|
volatile uint64_t *src = ((volatile uint64_t *)wqe);
|
|
|
|
rte_io_wmb();
|
|
*txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
|
|
/* Ensure ordering between DB record and BF copy. */
|
|
rte_wmb();
|
|
*dst = *src;
|
|
if (cond)
|
|
rte_wmb();
|
|
}
|
|
|
|
/**
|
|
* Ring TX queue doorbell and flush the update by write memory barrier.
|
|
*
|
|
* @param txq
|
|
* Pointer to TX queue structure.
|
|
* @param wqe
|
|
* Pointer to the last WQE posted in the NIC.
|
|
*/
|
|
static __rte_always_inline void
|
|
mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
|
|
{
|
|
mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
|
|
}
|
|
|
|
/**
|
|
* Convert the Checksum offloads to Verbs.
|
|
*
|
|
* @param txq_data
|
|
* Pointer to the Tx queue.
|
|
* @param buf
|
|
* Pointer to the mbuf.
|
|
*
|
|
* @return
|
|
* the converted cs_flags.
|
|
*/
|
|
static __rte_always_inline uint8_t
|
|
txq_ol_cksum_to_cs(struct mlx5_txq_data *txq_data, struct rte_mbuf *buf)
|
|
{
|
|
uint8_t cs_flags = 0;
|
|
|
|
/* Should we enable HW CKSUM offload */
|
|
if (buf->ol_flags &
|
|
(PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM |
|
|
PKT_TX_OUTER_IP_CKSUM)) {
|
|
if (txq_data->tunnel_en &&
|
|
(buf->ol_flags &
|
|
(PKT_TX_TUNNEL_GRE | PKT_TX_TUNNEL_VXLAN))) {
|
|
cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
|
|
MLX5_ETH_WQE_L4_INNER_CSUM;
|
|
if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
|
|
cs_flags |= MLX5_ETH_WQE_L3_CSUM;
|
|
} else {
|
|
cs_flags = MLX5_ETH_WQE_L3_CSUM |
|
|
MLX5_ETH_WQE_L4_CSUM;
|
|
}
|
|
}
|
|
return cs_flags;
|
|
}
|
|
|
|
/**
|
|
* Count the number of contiguous single segment packets.
|
|
*
|
|
* @param pkts
|
|
* Pointer to array of packets.
|
|
* @param pkts_n
|
|
* Number of packets.
|
|
*
|
|
* @return
|
|
* Number of contiguous single segment packets.
|
|
*/
|
|
static __rte_always_inline unsigned int
|
|
txq_count_contig_single_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
|
|
{
|
|
unsigned int pos;
|
|
|
|
if (!pkts_n)
|
|
return 0;
|
|
/* Count the number of contiguous single segment packets. */
|
|
for (pos = 0; pos < pkts_n; ++pos)
|
|
if (NB_SEGS(pkts[pos]) > 1)
|
|
break;
|
|
return pos;
|
|
}
|
|
|
|
/**
|
|
* Count the number of contiguous multi-segment packets.
|
|
*
|
|
* @param pkts
|
|
* Pointer to array of packets.
|
|
* @param pkts_n
|
|
* Number of packets.
|
|
*
|
|
* @return
|
|
* Number of contiguous multi-segment packets.
|
|
*/
|
|
static __rte_always_inline unsigned int
|
|
txq_count_contig_multi_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
|
|
{
|
|
unsigned int pos;
|
|
|
|
if (!pkts_n)
|
|
return 0;
|
|
/* Count the number of contiguous multi-segment packets. */
|
|
for (pos = 0; pos < pkts_n; ++pos)
|
|
if (NB_SEGS(pkts[pos]) == 1)
|
|
break;
|
|
return pos;
|
|
}
|
|
|
|
#endif /* RTE_PMD_MLX5_RXTX_H_ */
|