9526f3003e
1. Packet transmit function for both otx and otx2 are added. 2. Flushing transmit(command) queue when pending commands are more than maximum allowed value (currently 16). 3. Scatter gather support if the packet spans multiple buffers. Signed-off-by: Nalla Pradeep <pnalla@marvell.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
169 lines
4.7 KiB
C
169 lines
4.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 Marvell.
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*/
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#ifndef _OTX_EP_VF_H_
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#define _OTX_EP_VF_H_
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#define OTX_EP_RING_OFFSET (0x1ull << 17)
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/* OTX_EP VF IQ Registers */
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#define OTX_EP_R_IN_CONTROL_START (0x10000)
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#define OTX_EP_R_IN_ENABLE_START (0x10010)
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#define OTX_EP_R_IN_INSTR_BADDR_START (0x10020)
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#define OTX_EP_R_IN_INSTR_RSIZE_START (0x10030)
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#define OTX_EP_R_IN_INSTR_DBELL_START (0x10040)
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#define OTX_EP_R_IN_CNTS_START (0x10050)
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#define OTX_EP_R_IN_INT_LEVELS_START (0x10060)
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#define OTX_EP_R_IN_CONTROL(ring) \
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(OTX_EP_R_IN_CONTROL_START + ((ring) * OTX_EP_RING_OFFSET))
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#define OTX_EP_R_IN_ENABLE(ring) \
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(OTX_EP_R_IN_ENABLE_START + ((ring) * OTX_EP_RING_OFFSET))
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#define OTX_EP_R_IN_INSTR_BADDR(ring) \
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(OTX_EP_R_IN_INSTR_BADDR_START + ((ring) * OTX_EP_RING_OFFSET))
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#define OTX_EP_R_IN_INSTR_RSIZE(ring) \
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(OTX_EP_R_IN_INSTR_RSIZE_START + ((ring) * OTX_EP_RING_OFFSET))
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#define OTX_EP_R_IN_INSTR_DBELL(ring) \
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(OTX_EP_R_IN_INSTR_DBELL_START + ((ring) * OTX_EP_RING_OFFSET))
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#define OTX_EP_R_IN_CNTS(ring) \
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(OTX_EP_R_IN_CNTS_START + ((ring) * OTX_EP_RING_OFFSET))
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#define OTX_EP_R_IN_INT_LEVELS(ring) \
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(OTX_EP_R_IN_INT_LEVELS_START + ((ring) * OTX_EP_RING_OFFSET))
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/* OTX_EP VF IQ Masks */
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#define OTX_EP_R_IN_CTL_RPVF_MASK (0xF)
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#define OTX_EP_R_IN_CTL_RPVF_POS (48)
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#define OTX_EP_R_IN_CTL_IDLE (0x1ull << 28)
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#define OTX_EP_R_IN_CTL_RDSIZE (0x3ull << 25) /* Setting to max(4) */
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#define OTX_EP_R_IN_CTL_IS_64B (0x1ull << 24)
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#define OTX_EP_R_IN_CTL_ESR (0x1ull << 1)
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/* OTX_EP VF OQ Registers */
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#define OTX_EP_R_OUT_CNTS_START (0x10100)
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#define OTX_EP_R_OUT_INT_LEVELS_START (0x10110)
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#define OTX_EP_R_OUT_SLIST_BADDR_START (0x10120)
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#define OTX_EP_R_OUT_SLIST_RSIZE_START (0x10130)
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#define OTX_EP_R_OUT_SLIST_DBELL_START (0x10140)
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#define OTX_EP_R_OUT_CONTROL_START (0x10150)
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#define OTX_EP_R_OUT_ENABLE_START (0x10160)
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#define OTX_EP_R_OUT_CONTROL(ring) \
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(OTX_EP_R_OUT_CONTROL_START + ((ring) * OTX_EP_RING_OFFSET))
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#define OTX_EP_R_OUT_ENABLE(ring) \
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(OTX_EP_R_OUT_ENABLE_START + ((ring) * OTX_EP_RING_OFFSET))
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#define OTX_EP_R_OUT_SLIST_BADDR(ring) \
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(OTX_EP_R_OUT_SLIST_BADDR_START + ((ring) * OTX_EP_RING_OFFSET))
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#define OTX_EP_R_OUT_SLIST_RSIZE(ring) \
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(OTX_EP_R_OUT_SLIST_RSIZE_START + ((ring) * OTX_EP_RING_OFFSET))
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#define OTX_EP_R_OUT_SLIST_DBELL(ring) \
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(OTX_EP_R_OUT_SLIST_DBELL_START + ((ring) * OTX_EP_RING_OFFSET))
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#define OTX_EP_R_OUT_CNTS(ring) \
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(OTX_EP_R_OUT_CNTS_START + ((ring) * OTX_EP_RING_OFFSET))
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#define OTX_EP_R_OUT_INT_LEVELS(ring) \
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(OTX_EP_R_OUT_INT_LEVELS_START + ((ring) * OTX_EP_RING_OFFSET))
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/* OTX_EP VF OQ Masks */
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#define OTX_EP_R_OUT_CTL_IDLE (1ull << 36)
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#define OTX_EP_R_OUT_CTL_ES_I (1ull << 34)
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#define OTX_EP_R_OUT_CTL_NSR_I (1ull << 33)
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#define OTX_EP_R_OUT_CTL_ROR_I (1ull << 32)
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#define OTX_EP_R_OUT_CTL_ES_D (1ull << 30)
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#define OTX_EP_R_OUT_CTL_NSR_D (1ull << 29)
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#define OTX_EP_R_OUT_CTL_ROR_D (1ull << 28)
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#define OTX_EP_R_OUT_CTL_ES_P (1ull << 26)
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#define OTX_EP_R_OUT_CTL_NSR_P (1ull << 25)
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#define OTX_EP_R_OUT_CTL_ROR_P (1ull << 24)
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#define OTX_EP_R_OUT_CTL_IMODE (1ull << 23)
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#define PCI_DEVID_OCTEONTX_EP_VF 0xa303
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/* this is a static value set by SLI PF driver in octeon
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* No handshake is available
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* Change this if changing the value in SLI PF driver
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*/
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#define SDP_GBL_WMARK 0x100
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/* Optional PKI Instruction Header(PKI IH) */
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typedef union {
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uint64_t u64;
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struct {
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/** Tag Value */
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uint64_t tag:32;
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/** QPG Value */
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uint64_t qpg:11;
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/** Reserved1 */
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uint64_t reserved1:2;
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/** Tag type */
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uint64_t tagtype:2;
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/** Use Tag Type */
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uint64_t utt:1;
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/** Skip Length */
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uint64_t sl:8;
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/** Parse Mode */
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uint64_t pm:3;
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/** Reserved2 */
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uint64_t reserved2:1;
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/** Use QPG */
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uint64_t uqpg:1;
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/** Use Tag */
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uint64_t utag:1;
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/** Raw mode indicator 1 = RAW */
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uint64_t raw:1;
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/** Wider bit */
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uint64_t w:1;
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} s;
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} otx_ep_instr_pki_ih3_t;
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/* OTX_EP 64B instruction format */
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struct otx_ep_instr_64B {
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/* Pointer where the input data is available. */
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uint64_t dptr;
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/* OTX_EP Instruction Header. */
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union otx_ep_instr_ih ih;
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/* PKI Optional Instruction Header. */
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otx_ep_instr_pki_ih3_t pki_ih3;
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/** Pointer where the response for a RAW mode packet
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* will be written by OCTEON TX.
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*/
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uint64_t rptr;
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/* Input Request Header. */
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union otx_ep_instr_irh irh;
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/* Additional headers available in a 64-byte instruction. */
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uint64_t exhdr[3];
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};
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int
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otx_ep_vf_setup_device(struct otx_ep_device *otx_ep);
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#endif /*_OTX_EP_VF_H_ */
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