195981133a
Octeontx2 PMD's mailbox client uses device memory to send messages
to mailbox server in the admin function Linux kernel driver.
The device memory used for the mailbox communication needs to
be qualified as volatile memory type to avoid unaligned device
memory accesses because of compiler's memory access coalescing.
This patch modifies the mailbox request and responses as volatile
type which were non-volatile earlier and accessed from unaligned
memory addresses which resulted in bus errors on Fedora 30 with
gcc 9.1.1.
Fixes: 2b71657c86 ("common/octeontx2: add mbox request and response definition")
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
136 lines
4.3 KiB
C
136 lines
4.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#include "otx2_mempool.h"
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#define npa_dump(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__)
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static inline void
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npa_lf_pool_dump(__otx2_io struct npa_pool_s *pool)
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{
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npa_dump("W0: Stack base\t\t0x%"PRIx64"", pool->stack_base);
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npa_dump("W1: ena \t\t%d\nW1: nat_align \t\t%d\nW1: stack_caching \t%d",
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pool->ena, pool->nat_align, pool->stack_caching);
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npa_dump("W1: stack_way_mask\t%d\nW1: buf_offset\t\t%d",
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pool->stack_way_mask, pool->buf_offset);
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npa_dump("W1: buf_size \t\t%d", pool->buf_size);
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npa_dump("W2: stack_max_pages \t%d\nW2: stack_pages\t\t%d",
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pool->stack_max_pages, pool->stack_pages);
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npa_dump("W3: op_pc \t\t0x%"PRIx64"", (uint64_t)pool->op_pc);
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npa_dump("W4: stack_offset\t%d\nW4: shift\t\t%d\nW4: avg_level\t\t%d",
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pool->stack_offset, pool->shift, pool->avg_level);
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npa_dump("W4: avg_con \t\t%d\nW4: fc_ena\t\t%d\nW4: fc_stype\t\t%d",
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pool->avg_con, pool->fc_ena, pool->fc_stype);
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npa_dump("W4: fc_hyst_bits\t%d\nW4: fc_up_crossing\t%d",
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pool->fc_hyst_bits, pool->fc_up_crossing);
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npa_dump("W4: update_time\t\t%d\n", pool->update_time);
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npa_dump("W5: fc_addr\t\t0x%"PRIx64"\n", pool->fc_addr);
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npa_dump("W6: ptr_start\t\t0x%"PRIx64"\n", pool->ptr_start);
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npa_dump("W7: ptr_end\t\t0x%"PRIx64"\n", pool->ptr_end);
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npa_dump("W8: err_int\t\t%d\nW8: err_int_ena\t\t%d",
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pool->err_int, pool->err_int_ena);
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npa_dump("W8: thresh_int\t\t%d", pool->thresh_int);
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npa_dump("W8: thresh_int_ena\t%d\nW8: thresh_up\t\t%d",
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pool->thresh_int_ena, pool->thresh_up);
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npa_dump("W8: thresh_qint_idx\t%d\nW8: err_qint_idx\t%d",
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pool->thresh_qint_idx, pool->err_qint_idx);
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}
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static inline void
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npa_lf_aura_dump(__otx2_io struct npa_aura_s *aura)
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{
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npa_dump("W0: Pool addr\t\t0x%"PRIx64"\n", aura->pool_addr);
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npa_dump("W1: ena\t\t\t%d\nW1: pool caching\t%d\nW1: pool way mask\t%d",
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aura->ena, aura->pool_caching, aura->pool_way_mask);
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npa_dump("W1: avg con\t\t%d\nW1: pool drop ena\t%d",
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aura->avg_con, aura->pool_drop_ena);
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npa_dump("W1: aura drop ena\t%d", aura->aura_drop_ena);
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npa_dump("W1: bp_ena\t\t%d\nW1: aura drop\t\t%d\nW1: aura shift\t\t%d",
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aura->bp_ena, aura->aura_drop, aura->shift);
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npa_dump("W1: avg_level\t\t%d\n", aura->avg_level);
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npa_dump("W2: count\t\t%"PRIx64"\nW2: nix0_bpid\t\t%d",
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(uint64_t)aura->count, aura->nix0_bpid);
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npa_dump("W2: nix1_bpid\t\t%d", aura->nix1_bpid);
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npa_dump("W3: limit\t\t%"PRIx64"\nW3: bp\t\t\t%d\nW3: fc_ena\t\t%d\n",
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(uint64_t)aura->limit, aura->bp, aura->fc_ena);
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npa_dump("W3: fc_up_crossing\t%d\nW3: fc_stype\t\t%d",
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aura->fc_up_crossing, aura->fc_stype);
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npa_dump("W3: fc_hyst_bits\t%d", aura->fc_hyst_bits);
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npa_dump("W4: fc_addr\t\t0x%"PRIx64"\n", aura->fc_addr);
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npa_dump("W5: pool_drop\t\t%d\nW5: update_time\t\t%d",
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aura->pool_drop, aura->update_time);
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npa_dump("W5: err_int\t\t%d", aura->err_int);
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npa_dump("W5: err_int_ena\t\t%d\nW5: thresh_int\t\t%d",
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aura->err_int_ena, aura->thresh_int);
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npa_dump("W5: thresh_int_ena\t%d", aura->thresh_int_ena);
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npa_dump("W5: thresh_up\t\t%d\nW5: thresh_qint_idx\t%d",
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aura->thresh_up, aura->thresh_qint_idx);
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npa_dump("W5: err_qint_idx\t%d", aura->err_qint_idx);
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npa_dump("W6: thresh\t\t%"PRIx64"\n", (uint64_t)aura->thresh);
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}
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int
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otx2_mempool_ctx_dump(struct otx2_npa_lf *lf)
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{
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struct npa_aq_enq_req *aq;
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struct npa_aq_enq_rsp *rsp;
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uint32_t q;
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int rc = 0;
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for (q = 0; q < lf->nr_pools; q++) {
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/* Skip disabled POOL */
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if (rte_bitmap_get(lf->npa_bmp, q))
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continue;
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aq = otx2_mbox_alloc_msg_npa_aq_enq(lf->mbox);
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aq->aura_id = q;
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aq->ctype = NPA_AQ_CTYPE_POOL;
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aq->op = NPA_AQ_INSTOP_READ;
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rc = otx2_mbox_process_msg(lf->mbox, (void *)&rsp);
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if (rc) {
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otx2_err("Failed to get pool(%d) context", q);
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return rc;
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}
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npa_dump("============== pool=%d ===============\n", q);
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npa_lf_pool_dump(&rsp->pool);
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}
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for (q = 0; q < lf->nr_pools; q++) {
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/* Skip disabled AURA */
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if (rte_bitmap_get(lf->npa_bmp, q))
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continue;
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aq = otx2_mbox_alloc_msg_npa_aq_enq(lf->mbox);
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aq->aura_id = q;
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aq->ctype = NPA_AQ_CTYPE_AURA;
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aq->op = NPA_AQ_INSTOP_READ;
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rc = otx2_mbox_process_msg(lf->mbox, (void *)&rsp);
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if (rc) {
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otx2_err("Failed to get aura(%d) context", q);
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return rc;
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}
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npa_dump("============== aura=%d ===============\n", q);
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npa_lf_aura_dump(&rsp->aura);
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}
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return rc;
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}
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