numam-dpdk/lib
Yuanhan Liu d948f596fe ethdev: fix port data mismatched in multiple process model
Assume we have two virtio ports, 00:03.0 and 00:04.0. The first one is
managed by the kernel driver, while the later one is managed by DPDK.

Now we start the primary process. 00:03.0 will be skipped by DPDK virtio
PMD driver (since it's being used by the kernel). 00:04.0 would be
successfully initiated by DPDK virtio PMD (if nothing abnormal happens).
After that, we would get a port id 0, and all the related info needed
by virtio (virtio_hw) is stored at rte_eth_dev_data[0].

Then we start the secondary process. As usual, 00:03.0 will be firstly
probed. It firstly tries to get a local eth_dev structure for it (by
rte_eth_dev_allocate):

        port_id = rte_eth_dev_find_free_port();
        ...

        eth_dev = &rte_eth_devices[port_id];
        eth_dev->data = &rte_eth_dev_data[port_id];
        ...

        return eth_dev;

Since it's a first PCI device, port_id will be 0. eth_dev->data would
then point to rte_eth_dev_data[0]. And here things start going wrong,
as rte_eth_dev_data[0] actually stores the virtio_hw for 00:04.0.

That said, in the secondary process, DPDK will continue to drive PCI
device 00.03.0 (despite the fact it's been managed by kernel), with
the info from PCI device 00:04.0. Which is wrong.

The fix is to attach the port already registered by the primary process.
That is, iterate the rte_eth_dev_data[], and get the port id who's PCI
ID matches the current PCI device.

This would let us maintain same port ID for the same PCI device, keeping
the chance of referencing to wrong data minimal.

Fixes: af75078fec ("first public release")
Cc: stable@dpdk.org

Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Acked-by: Thomas Monjalon <thomas.monjalon@6wind.com>
2017-01-17 09:20:18 +01:00
..
librte_acl lib: use C99 syntax for zero-size arrays 2016-09-13 15:35:28 +02:00
librte_cfgfile cfgfile: fix API comments 2016-11-06 23:34:40 +01:00
librte_cmdline cmdline: add alignment constraint 2016-12-23 10:19:11 +01:00
librte_compat compat: remove unneeded macro 2015-06-29 16:41:23 +02:00
librte_cryptodev cryptodev: clarify how operations affect buffers 2016-11-07 00:22:58 +01:00
librte_distributor distributor: remove inclusion of mbuf header 2015-05-11 15:36:37 +02:00
librte_eal pci: use address struct in function arguments 2017-01-12 15:55:16 +01:00
librte_ether ethdev: fix port data mismatched in multiple process model 2017-01-17 09:20:18 +01:00
librte_hash hash: fix bucket size usage 2016-10-12 18:40:52 +02:00
librte_ip_frag ip_frag: fix IP reassembly regression 2016-11-07 21:27:50 +01:00
librte_jobstats jobstats: fix typo in a comment 2016-06-30 18:51:20 +02:00
librte_kni doc: fix typos 2016-11-07 21:50:27 +01:00
librte_kvargs kvargs: make pointers in string arrays const 2017-01-13 19:28:26 +01:00
librte_lpm lpm: fix freeing memory 2016-11-06 23:46:03 +01:00
librte_mbuf mbuf: add a function to linearize a packet 2017-01-15 19:30:00 +01:00
librte_mempool mempool: use cache in single producer or consumer mode 2017-01-13 16:38:09 +01:00
librte_meter meter: fix excess token bucket update in srtcm 2016-09-21 22:56:03 +02:00
librte_net ethdev: add Tx preparation 2017-01-04 20:40:15 +01:00
librte_pdump doc: add pdump library to API doxygen 2016-12-06 15:43:13 +01:00
librte_pipeline lib: work around unnamed structs/unions 2016-09-13 15:35:28 +02:00
librte_port port: support file descriptor 2016-10-13 11:42:37 +02:00
librte_power examples/vm_power_manager: remove dependency on internal header 2016-07-11 17:23:32 +02:00
librte_reorder lib: add missing include dependencies 2016-09-13 15:35:28 +02:00
librte_ring doc: fix typos in code comments 2016-12-06 15:25:01 +01:00
librte_sched sched: fix releasing enqueued packets 2016-09-23 21:14:54 +02:00
librte_table table: add cuckoo hash 2016-10-12 22:08:36 +02:00
librte_timer timer: fix lag delay 2016-10-05 12:02:53 +02:00
librte_vhost vhost: allow many vhost-user ports 2017-01-17 09:20:18 +01:00
Makefile ivshmem: remove library and its EAL integration 2016-08-23 12:23:58 +02:00