e66eda1c24
Replace the raw I/O device memory read/write access with eal abstraction for I/O device memory read/write access to fix portability issues across different architectures. CC: Wenzhuo Lu <wenzhuo.lu@intel.com> Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
199 lines
6.4 KiB
C
199 lines
6.4 KiB
C
/******************************************************************************
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Copyright (c) 2001-2014, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#ifndef _E1000_OSDEP_H_
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#define _E1000_OSDEP_H_
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#include <stdint.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <rte_common.h>
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#include <rte_cycles.h>
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#include <rte_log.h>
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#include <rte_debug.h>
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#include <rte_byteorder.h>
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#include <rte_io.h>
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#include "../e1000_logs.h"
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#define DELAY(x) rte_delay_us(x)
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#define usec_delay(x) DELAY(x)
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#define usec_delay_irq(x) DELAY(x)
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#define msec_delay(x) DELAY(1000*(x))
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#define msec_delay_irq(x) DELAY(1000*(x))
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#define DEBUGFUNC(F) DEBUGOUT(F "\n");
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#define DEBUGOUT(S, args...) PMD_DRV_LOG_RAW(DEBUG, S, ##args)
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#define DEBUGOUT1(S, args...) DEBUGOUT(S, ##args)
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#define DEBUGOUT2(S, args...) DEBUGOUT(S, ##args)
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#define DEBUGOUT3(S, args...) DEBUGOUT(S, ##args)
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#define DEBUGOUT6(S, args...) DEBUGOUT(S, ##args)
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#define DEBUGOUT7(S, args...) DEBUGOUT(S, ##args)
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#define UNREFERENCED_PARAMETER(_p)
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#define UNREFERENCED_1PARAMETER(_p)
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#define UNREFERENCED_2PARAMETER(_p, _q)
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#define UNREFERENCED_3PARAMETER(_p, _q, _r)
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#define UNREFERENCED_4PARAMETER(_p, _q, _r, _s)
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#define FALSE 0
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#define TRUE 1
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#define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
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/* Mutex used in the shared code */
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#define E1000_MUTEX uintptr_t
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#define E1000_MUTEX_INIT(mutex) (*(mutex) = 0)
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#define E1000_MUTEX_LOCK(mutex) (*(mutex) = 1)
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#define E1000_MUTEX_UNLOCK(mutex) (*(mutex) = 0)
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typedef uint64_t u64;
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typedef uint32_t u32;
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typedef uint16_t u16;
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typedef uint8_t u8;
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typedef int64_t s64;
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typedef int32_t s32;
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typedef int16_t s16;
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typedef int8_t s8;
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typedef int bool;
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#define __le16 u16
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#define __le32 u32
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#define __le64 u64
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#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
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#define E1000_PCI_REG(reg) rte_read32(reg)
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#define E1000_PCI_REG16(reg) rte_read16(reg)
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#define E1000_PCI_REG_WRITE(reg, value) \
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rte_write32((rte_cpu_to_le_32(value)), reg)
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#define E1000_PCI_REG_WRITE_RELAXED(reg, value) \
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rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
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#define E1000_PCI_REG_WRITE16(reg, value) \
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rte_write16((rte_cpu_to_le_16(value)), reg)
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#define E1000_PCI_REG_ADDR(hw, reg) \
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((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
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#define E1000_PCI_REG_ARRAY_ADDR(hw, reg, index) \
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E1000_PCI_REG_ADDR((hw), (reg) + ((index) << 2))
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#define E1000_PCI_REG_FLASH_ADDR(hw, reg) \
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((volatile uint32_t *)((char *)(hw)->flash_address + (reg)))
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static inline uint32_t e1000_read_addr(volatile void *addr)
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{
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return rte_le_to_cpu_32(E1000_PCI_REG(addr));
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}
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static inline uint16_t e1000_read_addr16(volatile void *addr)
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{
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return rte_le_to_cpu_16(E1000_PCI_REG16(addr));
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}
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/* Necessary defines */
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#define E1000_MRQC_ENABLE_MASK 0x00000007
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#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
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#define E1000_ALL_FULL_DUPLEX ( \
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ADVERTISE_10_FULL | ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
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#define M88E1543_E_PHY_ID 0x01410EA0
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#define ULP_SUPPORT
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#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
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#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
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/* Register READ/WRITE macros */
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#define E1000_READ_REG(hw, reg) \
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e1000_read_addr(E1000_PCI_REG_ADDR((hw), (reg)))
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#define E1000_WRITE_REG(hw, reg, value) \
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E1000_PCI_REG_WRITE(E1000_PCI_REG_ADDR((hw), (reg)), (value))
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#define E1000_READ_REG_ARRAY(hw, reg, index) \
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E1000_PCI_REG(E1000_PCI_REG_ARRAY_ADDR((hw), (reg), (index)))
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#define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \
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E1000_PCI_REG_WRITE(E1000_PCI_REG_ARRAY_ADDR((hw), (reg), (index)), (value))
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#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
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#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
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#define E1000_ACCESS_PANIC(x, hw, reg, value) \
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rte_panic("%s:%u\t" RTE_STR(x) "(%p, 0x%x, 0x%x)", \
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__FILE__, __LINE__, (hw), (reg), (unsigned int)(value))
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/*
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* To be able to do IO write, we need to map IO BAR
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* (bar 2/4 depending on device).
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* Right now mapping multiple BARs is not supported by DPDK.
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* Fortunatelly we need it only for legacy hw support.
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*/
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#define E1000_WRITE_REG_IO(hw, reg, value) \
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E1000_WRITE_REG(hw, reg, value)
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/*
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* Tested on I217/I218 chipset.
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*/
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#define E1000_READ_FLASH_REG(hw, reg) \
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e1000_read_addr(E1000_PCI_REG_FLASH_ADDR((hw), (reg)))
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#define E1000_READ_FLASH_REG16(hw, reg) \
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e1000_read_addr16(E1000_PCI_REG_FLASH_ADDR((hw), (reg)))
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#define E1000_WRITE_FLASH_REG(hw, reg, value) \
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E1000_PCI_REG_WRITE(E1000_PCI_REG_FLASH_ADDR((hw), (reg)), (value))
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#define E1000_WRITE_FLASH_REG16(hw, reg, value) \
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E1000_PCI_REG_WRITE16(E1000_PCI_REG_FLASH_ADDR((hw), (reg)), (value))
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#define STATIC static
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#ifndef ETH_ADDR_LEN
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#define ETH_ADDR_LEN 6
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#endif
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#define false FALSE
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#define true TRUE
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#endif /* _E1000_OSDEP_H_ */
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