d8dd31652c
Move commonly used functions across mempool, event and net devices to a common folder in drivers. Signed-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com> Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> Acked-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
291 lines
6.3 KiB
C
291 lines
6.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2017 Cavium, Inc
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*/
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#include <rte_atomic.h>
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#include <rte_common.h>
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#include <rte_eal.h>
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#include <rte_io.h>
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#include <rte_pci.h>
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#include <rte_bus_pci.h>
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#include "octeontx_mbox.h"
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#include "ssovf_evdev.h"
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#define PCI_VENDOR_ID_CAVIUM 0x177D
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#define PCI_DEVICE_ID_OCTEONTX_SSOGRP_VF 0xA04B
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#define PCI_DEVICE_ID_OCTEONTX_SSOWS_VF 0xA04D
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#define SSO_MAX_VHGRP (64)
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#define SSO_MAX_VHWS (32)
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#define SSO_VHGRP_AQ_THR (0x1E0ULL)
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struct ssovf_res {
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uint16_t domain;
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uint16_t vfid;
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void *bar0;
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void *bar2;
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};
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struct ssowvf_res {
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uint16_t domain;
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uint16_t vfid;
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void *bar0;
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void *bar2;
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void *bar4;
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};
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struct ssowvf_identify {
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uint16_t domain;
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uint16_t vfid;
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};
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struct ssodev {
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uint8_t total_ssovfs;
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uint8_t total_ssowvfs;
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struct ssovf_res grp[SSO_MAX_VHGRP];
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struct ssowvf_res hws[SSO_MAX_VHWS];
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};
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static struct ssodev sdev;
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/* Interface functions */
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int
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ssovf_info(struct ssovf_info *info)
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{
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uint8_t i;
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uint16_t domain;
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if (rte_eal_process_type() != RTE_PROC_PRIMARY || info == NULL)
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return -EINVAL;
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if (sdev.total_ssovfs == 0 || sdev.total_ssowvfs == 0)
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return -ENODEV;
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domain = sdev.grp[0].domain;
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for (i = 0; i < sdev.total_ssovfs; i++) {
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/* Check vfid's are contiguous and belong to same domain */
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if (sdev.grp[i].vfid != i ||
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sdev.grp[i].bar0 == NULL ||
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sdev.grp[i].domain != domain) {
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mbox_log_err("GRP error, vfid=%d/%d domain=%d/%d %p",
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i, sdev.grp[i].vfid,
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domain, sdev.grp[i].domain,
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sdev.grp[i].bar0);
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return -EINVAL;
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}
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}
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for (i = 0; i < sdev.total_ssowvfs; i++) {
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/* Check vfid's are contiguous and belong to same domain */
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if (sdev.hws[i].vfid != i ||
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sdev.hws[i].bar0 == NULL ||
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sdev.hws[i].domain != domain) {
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mbox_log_err("HWS error, vfid=%d/%d domain=%d/%d %p",
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i, sdev.hws[i].vfid,
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domain, sdev.hws[i].domain,
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sdev.hws[i].bar0);
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return -EINVAL;
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}
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}
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info->domain = domain;
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info->total_ssovfs = sdev.total_ssovfs;
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info->total_ssowvfs = sdev.total_ssowvfs;
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return 0;
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}
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void*
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ssovf_bar(enum ssovf_type type, uint8_t id, uint8_t bar)
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{
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if (rte_eal_process_type() != RTE_PROC_PRIMARY ||
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type > OCTEONTX_SSO_HWS)
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return NULL;
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if (type == OCTEONTX_SSO_GROUP) {
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if (id >= sdev.total_ssovfs)
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return NULL;
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} else {
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if (id >= sdev.total_ssowvfs)
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return NULL;
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}
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if (type == OCTEONTX_SSO_GROUP) {
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switch (bar) {
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case 0:
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return sdev.grp[id].bar0;
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case 2:
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return sdev.grp[id].bar2;
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default:
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return NULL;
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}
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} else {
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switch (bar) {
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case 0:
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return sdev.hws[id].bar0;
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case 2:
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return sdev.hws[id].bar2;
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case 4:
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return sdev.hws[id].bar4;
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default:
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return NULL;
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}
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}
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}
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/* SSOWVF pcie device aka event port probe */
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static int
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ssowvf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
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{
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uint16_t vfid;
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struct ssowvf_res *res;
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struct ssowvf_identify *id;
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uint8_t *ram_mbox_base;
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RTE_SET_USED(pci_drv);
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/* For secondary processes, the primary has done all the work */
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if (rte_eal_process_type() != RTE_PROC_PRIMARY)
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return 0;
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if (pci_dev->mem_resource[0].addr == NULL ||
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pci_dev->mem_resource[2].addr == NULL ||
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pci_dev->mem_resource[4].addr == NULL) {
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mbox_log_err("Empty bars %p %p %p",
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pci_dev->mem_resource[0].addr,
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pci_dev->mem_resource[2].addr,
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pci_dev->mem_resource[4].addr);
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return -ENODEV;
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}
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if (pci_dev->mem_resource[4].len != SSOW_BAR4_LEN) {
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mbox_log_err("Bar4 len mismatch %d != %d",
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SSOW_BAR4_LEN, (int)pci_dev->mem_resource[4].len);
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return -EINVAL;
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}
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id = pci_dev->mem_resource[4].addr;
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vfid = id->vfid;
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if (vfid >= SSO_MAX_VHWS) {
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mbox_log_err("Invalid vfid(%d/%d)", vfid, SSO_MAX_VHWS);
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return -EINVAL;
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}
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res = &sdev.hws[vfid];
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res->vfid = vfid;
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res->bar0 = pci_dev->mem_resource[0].addr;
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res->bar2 = pci_dev->mem_resource[2].addr;
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res->bar4 = pci_dev->mem_resource[4].addr;
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res->domain = id->domain;
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sdev.total_ssowvfs++;
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if (vfid == 0) {
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ram_mbox_base = ssovf_bar(OCTEONTX_SSO_HWS, 0, 4);
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if (octeontx_mbox_set_ram_mbox_base(ram_mbox_base)) {
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mbox_log_err("Invalid Failed to set ram mbox base");
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return -EINVAL;
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}
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}
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rte_wmb();
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mbox_log_dbg("Domain=%d hws=%d total_ssowvfs=%d", res->domain,
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res->vfid, sdev.total_ssowvfs);
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return 0;
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}
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static const struct rte_pci_id pci_ssowvf_map[] = {
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{
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RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
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PCI_DEVICE_ID_OCTEONTX_SSOWS_VF)
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},
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{
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.vendor_id = 0,
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},
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};
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static struct rte_pci_driver pci_ssowvf = {
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.id_table = pci_ssowvf_map,
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.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
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.probe = ssowvf_probe,
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};
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RTE_PMD_REGISTER_PCI(octeontx_ssowvf, pci_ssowvf);
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/* SSOVF pcie device aka event queue probe */
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static int
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ssovf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
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{
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uint64_t val;
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uint16_t vfid;
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uint8_t *idreg;
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struct ssovf_res *res;
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uint8_t *reg;
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RTE_SET_USED(pci_drv);
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/* For secondary processes, the primary has done all the work */
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if (rte_eal_process_type() != RTE_PROC_PRIMARY)
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return 0;
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if (pci_dev->mem_resource[0].addr == NULL ||
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pci_dev->mem_resource[2].addr == NULL) {
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mbox_log_err("Empty bars %p %p",
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pci_dev->mem_resource[0].addr,
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pci_dev->mem_resource[2].addr);
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return -ENODEV;
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}
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idreg = pci_dev->mem_resource[0].addr;
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idreg += SSO_VHGRP_AQ_THR;
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val = rte_read64(idreg);
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/* Write back the default value of aq_thr */
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rte_write64((1ULL << 33) - 1, idreg);
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vfid = (val >> 16) & 0xffff;
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if (vfid >= SSO_MAX_VHGRP) {
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mbox_log_err("Invalid vfid (%d/%d)", vfid, SSO_MAX_VHGRP);
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return -EINVAL;
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}
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res = &sdev.grp[vfid];
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res->vfid = vfid;
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res->bar0 = pci_dev->mem_resource[0].addr;
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res->bar2 = pci_dev->mem_resource[2].addr;
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res->domain = val & 0xffff;
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sdev.total_ssovfs++;
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if (vfid == 0) {
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reg = ssovf_bar(OCTEONTX_SSO_GROUP, 0, 0);
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reg += SSO_VHGRP_PF_MBOX(1);
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if (octeontx_mbox_set_reg(reg)) {
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mbox_log_err("Invalid Failed to set mbox_reg");
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return -EINVAL;
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}
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}
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rte_wmb();
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mbox_log_dbg("Domain=%d group=%d total_ssovfs=%d", res->domain,
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res->vfid, sdev.total_ssovfs);
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return 0;
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}
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static const struct rte_pci_id pci_ssovf_map[] = {
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{
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RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
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PCI_DEVICE_ID_OCTEONTX_SSOGRP_VF)
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},
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{
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.vendor_id = 0,
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},
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};
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static struct rte_pci_driver pci_ssovf = {
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.id_table = pci_ssovf_map,
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.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
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.probe = ssovf_probe,
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};
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RTE_PMD_REGISTER_PCI(octeontx_ssovf, pci_ssovf);
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