3bd122eef2
Adds hardware specific api for all the Chelsio T5 adapters under drivers/net/cxgbe/base directory. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
150 lines
4.6 KiB
C
150 lines
4.6 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright(c) 2014-2015 Chelsio Communications.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Chelsio Communications nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __T4_HW_H
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#define __T4_HW_H
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enum {
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NCHAN = 4, /* # of HW channels */
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NMTUS = 16, /* size of MTU table */
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NCCTRL_WIN = 32, /* # of congestion control windows */
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MBOX_LEN = 64, /* mailbox size in bytes */
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UDBS_SEG_SIZE = 128, /* segment size for BAR2 user doorbells */
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};
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enum {
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CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
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};
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enum {
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SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
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};
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enum {
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SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
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SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
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};
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/* PCI-e memory window access */
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enum pcie_memwin {
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MEMWIN_NIC = 0,
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};
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enum {
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SGE_MAX_WR_LEN = 512, /* max WR size in bytes */
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SGE_EQ_IDXSIZE = 64, /* egress queue pidx/cidx unit size */
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/* max no. of desc allowed in WR */
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SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / SGE_EQ_IDXSIZE,
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};
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struct sge_qstat { /* data written to SGE queue status entries */
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__be32 qid;
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__be16 cidx;
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__be16 pidx;
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};
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/*
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* Structure for last 128 bits of response descriptors
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*/
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struct rsp_ctrl {
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__be32 hdrbuflen_pidx;
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__be32 pldbuflen_qid;
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union {
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u8 type_gen;
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__be64 last_flit;
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} u;
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};
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#define S_RSPD_NEWBUF 31
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#define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF)
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#define F_RSPD_NEWBUF V_RSPD_NEWBUF(1U)
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#define S_RSPD_LEN 0
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#define M_RSPD_LEN 0x7fffffff
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#define V_RSPD_LEN(x) ((x) << S_RSPD_LEN)
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#define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN)
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#define S_RSPD_GEN 7
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#define V_RSPD_GEN(x) ((x) << S_RSPD_GEN)
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#define F_RSPD_GEN V_RSPD_GEN(1U)
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#define S_RSPD_TYPE 4
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#define M_RSPD_TYPE 0x3
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#define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE)
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#define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE)
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/* Rx queue interrupt deferral field: timer index */
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#define S_QINTR_CNT_EN 0
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#define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN)
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#define F_QINTR_CNT_EN V_QINTR_CNT_EN(1U)
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#define S_QINTR_TIMER_IDX 1
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#define M_QINTR_TIMER_IDX 0x7
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#define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX)
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#define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX)
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/*
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* Flash layout.
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*/
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#define FLASH_START(start) ((start) * SF_SEC_SIZE)
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#define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)
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enum {
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/*
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* Location of firmware image in FLASH.
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*/
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FLASH_FW_START_SEC = 8,
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FLASH_FW_NSECS = 16,
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FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
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FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
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/*
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* Location of Firmware Configuration File in FLASH.
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*/
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FLASH_CFG_START_SEC = 31,
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FLASH_CFG_NSECS = 1,
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FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
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FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
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/*
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* We don't support FLASH devices which can't support the full
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* standard set of sections which we need for normal operations.
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*/
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FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
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};
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#undef FLASH_START
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#undef FLASH_MAX_SIZE
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#endif /* __T4_HW_H */
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