6353ff43a7
Windows compilation gives us a splat:
In file included from ../drivers/dma/idxd/idxd_pci.c:10:
In file included from ..\drivers\dma\idxd/idxd_internal.h:11:
..\drivers\dma\idxd/idxd_hw_defs.h:46:21: error: expected member name or
';' after declaration specifiers
uint16_t __reserved[13];
~~~~~~~~ ^
1 error generated.
Ironically, __reserved is probably a reserved token.
Some drivers that build fine on Windows have structs with a "reserved"
field, let's go with this.
Fixes: 82147042d0 ("dma/idxd: add datapath structures")
Signed-off-by: David Marchand <david.marchand@redhat.com>
132 lines
3.7 KiB
C
132 lines
3.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2021 Intel Corporation
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*/
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#ifndef _IDXD_HW_DEFS_H_
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#define _IDXD_HW_DEFS_H_
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/*
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* Defines used in the data path for interacting with IDXD hardware.
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*/
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#define IDXD_CMD_OP_SHIFT 24
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enum rte_idxd_ops {
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idxd_op_nop = 0,
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idxd_op_batch,
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idxd_op_drain,
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idxd_op_memmove,
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idxd_op_fill
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};
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#define IDXD_FLAG_FENCE (1 << 0)
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#define IDXD_FLAG_COMPLETION_ADDR_VALID (1 << 2)
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#define IDXD_FLAG_REQUEST_COMPLETION (1 << 3)
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#define IDXD_FLAG_CACHE_CONTROL (1 << 8)
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/**
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* Hardware descriptor used by DSA hardware, for both bursts and
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* for individual operations.
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*/
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struct idxd_hw_desc {
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uint32_t pasid;
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uint32_t op_flags;
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rte_iova_t completion;
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RTE_STD_C11
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union {
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rte_iova_t src; /* source address for copy ops etc. */
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rte_iova_t desc_addr; /* descriptor pointer for batch */
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};
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rte_iova_t dst;
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uint32_t size; /* length of data for op, or batch size */
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uint16_t intr_handle; /* completion interrupt handle */
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/* remaining 26 bytes are reserved */
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uint16_t reserved[13];
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} __rte_aligned(64);
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#define IDXD_COMP_STATUS_INCOMPLETE 0
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#define IDXD_COMP_STATUS_SUCCESS 1
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#define IDXD_COMP_STATUS_INVALID_OPCODE 0x10
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#define IDXD_COMP_STATUS_INVALID_SIZE 0x13
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#define IDXD_COMP_STATUS_SKIPPED 0xFF /* not official IDXD error, needed as placeholder */
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/**
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* Completion record structure written back by DSA
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*/
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struct idxd_completion {
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uint8_t status;
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uint8_t result;
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/* 16-bits pad here */
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uint32_t completed_size; /* data length, or descriptors for batch */
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rte_iova_t fault_address;
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uint32_t invalid_flags;
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} __rte_aligned(32);
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/*** Definitions for Intel(R) Data Streaming Accelerator ***/
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#define IDXD_CMD_SHIFT 20
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enum rte_idxd_cmds {
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idxd_enable_dev = 1,
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idxd_disable_dev,
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idxd_drain_all,
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idxd_abort_all,
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idxd_reset_device,
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idxd_enable_wq,
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idxd_disable_wq,
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idxd_drain_wq,
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idxd_abort_wq,
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idxd_reset_wq,
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};
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/* General bar0 registers */
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struct rte_idxd_bar0 {
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uint32_t __rte_cache_aligned version; /* offset 0x00 */
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uint64_t __rte_aligned(0x10) gencap; /* offset 0x10 */
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uint64_t __rte_aligned(0x10) wqcap; /* offset 0x20 */
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uint64_t __rte_aligned(0x10) grpcap; /* offset 0x30 */
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uint64_t __rte_aligned(0x08) engcap; /* offset 0x38 */
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uint64_t __rte_aligned(0x10) opcap; /* offset 0x40 */
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uint64_t __rte_aligned(0x20) offsets[2]; /* offset 0x60 */
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uint32_t __rte_aligned(0x20) gencfg; /* offset 0x80 */
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uint32_t __rte_aligned(0x08) genctrl; /* offset 0x88 */
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uint32_t __rte_aligned(0x10) gensts; /* offset 0x90 */
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uint32_t __rte_aligned(0x08) intcause; /* offset 0x98 */
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uint32_t __rte_aligned(0x10) cmd; /* offset 0xA0 */
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uint32_t __rte_aligned(0x08) cmdstatus; /* offset 0xA8 */
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uint64_t __rte_aligned(0x20) swerror[4]; /* offset 0xC0 */
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};
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/* workqueue config is provided by array of uint32_t. */
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enum rte_idxd_wqcfg {
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wq_size_idx, /* size is in first 32-bit value */
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wq_threshold_idx, /* WQ threshold second 32-bits */
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wq_mode_idx, /* WQ mode and other flags */
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wq_sizes_idx, /* WQ transfer and batch sizes */
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wq_occ_int_idx, /* WQ occupancy interrupt handle */
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wq_occ_limit_idx, /* WQ occupancy limit */
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wq_state_idx, /* WQ state and occupancy state */
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};
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#define WQ_MODE_SHARED 0
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#define WQ_MODE_DEDICATED 1
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#define WQ_PRIORITY_SHIFT 4
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#define WQ_BATCH_SZ_SHIFT 5
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#define WQ_STATE_SHIFT 30
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#define WQ_STATE_MASK 0x3
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struct rte_idxd_grpcfg {
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uint64_t grpwqcfg[4] __rte_cache_aligned; /* 64-byte register set */
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uint64_t grpengcfg; /* offset 32 */
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uint32_t grpflags; /* offset 40 */
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};
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#define GENSTS_DEV_STATE_MASK 0x03
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#define CMDSTATUS_ACTIVE_SHIFT 31
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#define CMDSTATUS_ACTIVE_MASK (1 << 31)
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#define CMDSTATUS_ERR_MASK 0xFF
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#endif
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