fa8f86a14e
Add meson build infrastructure along with HW definition header file. This patch also adds cross-compile configs for arm for CN9K series and CN10K series of Marvell SoC's. Signed-off-by: Jerin Jacob <jerinj@marvell.com> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by: Sunil Kumar Kori <skori@marvell.com> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com> Signed-off-by: Satha Rao <skoteshwar@marvell.com> Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
16 lines
421 B
C
16 lines
421 B
C
/* SPDX-License-Identifier: BSD-3-Clause
|
|
* Copyright(C) 2021 Marvell.
|
|
*/
|
|
|
|
#ifndef _ROC_BITFIELD_H_
|
|
#define _ROC_BITFIELD_H_
|
|
|
|
#define __bf_shf(x) (__builtin_ffsll(x) - 1)
|
|
|
|
#define FIELD_PREP(mask, val) (((typeof(mask))(val) << __bf_shf(mask)) & (mask))
|
|
|
|
#define FIELD_GET(mask, reg) \
|
|
((typeof(mask))(((reg) & (mask)) >> __bf_shf(mask)))
|
|
|
|
#endif /* _ROC_BITFIELD_H_ */
|