dac12650eb
Add support to retrieve dev infos get for CN9K and CN10K. Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
119 lines
3.5 KiB
C
119 lines
3.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 Marvell.
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*/
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#ifndef __CNXK_ETHDEV_H__
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#define __CNXK_ETHDEV_H__
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#include <math.h>
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#include <stdint.h>
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#include <ethdev_driver.h>
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#include <ethdev_pci.h>
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#include <rte_kvargs.h>
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#include "roc_api.h"
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#define CNXK_ETH_DEV_PMD_VERSION "1.0"
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/* VLAN tag inserted by NIX_TX_VTAG_ACTION.
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* In Tx space is always reserved for this in FRS.
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*/
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#define CNXK_NIX_MAX_VTAG_INS 2
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#define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS)
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/* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
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#define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
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#define CNXK_NIX_RX_MIN_DESC 16
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#define CNXK_NIX_RX_MIN_DESC_ALIGN 16
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#define CNXK_NIX_RX_NB_SEG_MAX 6
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#define CNXK_NIX_RX_DEFAULT_RING_SZ 4096
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/* Max supported SQB count */
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#define CNXK_NIX_TX_MAX_SQB 512
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/* If PTP is enabled additional SEND MEM DESC is required which
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* takes 2 words, hence max 7 iova address are possible
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*/
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#if defined(RTE_LIBRTE_IEEE1588)
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#define CNXK_NIX_TX_NB_SEG_MAX 7
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#else
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#define CNXK_NIX_TX_NB_SEG_MAX 9
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#endif
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#define CNXK_NIX_RSS_L3_L4_SRC_DST \
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(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY | \
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ETH_RSS_L4_DST_ONLY)
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#define CNXK_NIX_RSS_OFFLOAD \
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(ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP | \
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ETH_RSS_SCTP | ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \
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CNXK_NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | ETH_RSS_C_VLAN)
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#define CNXK_NIX_TX_OFFLOAD_CAPA \
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(DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE | \
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DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT | \
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DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
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DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM | \
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DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO | \
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DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
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DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS | \
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DEV_TX_OFFLOAD_IPV4_CKSUM)
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#define CNXK_NIX_RX_OFFLOAD_CAPA \
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(DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM | \
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DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER | \
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DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
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DEV_RX_OFFLOAD_RSS_HASH)
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struct cnxk_eth_dev {
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/* ROC NIX */
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struct roc_nix nix;
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/* Max macfilter entries */
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uint8_t max_mac_entries;
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uint16_t flags;
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bool scalar_ena;
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/* Pointer back to rte */
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struct rte_eth_dev *eth_dev;
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/* HW capabilities / Limitations */
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union {
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struct {
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uint64_t cq_min_4k : 1;
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};
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uint64_t hwcap;
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};
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/* Rx and Tx offload capabilities */
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uint64_t rx_offload_capa;
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uint64_t tx_offload_capa;
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uint32_t speed_capa;
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/* Default mac address */
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uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
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};
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static inline struct cnxk_eth_dev *
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cnxk_eth_pmd_priv(struct rte_eth_dev *eth_dev)
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{
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return eth_dev->data->dev_private;
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}
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/* Common ethdev ops */
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extern struct eth_dev_ops cnxk_eth_dev_ops;
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/* Ops */
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int cnxk_nix_probe(struct rte_pci_driver *pci_drv,
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struct rte_pci_device *pci_dev);
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int cnxk_nix_remove(struct rte_pci_device *pci_dev);
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int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,
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struct rte_eth_dev_info *dev_info);
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/* Devargs */
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int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
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struct cnxk_eth_dev *dev);
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#endif /* __CNXK_ETHDEV_H__ */
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