46bc9d7513
When using multiple processes, the TX function used in all processes should be the same, otherwise the secondary processes cannot transmit more than tx-ring-size - 1 packets. To achieve this, we extract out the code to select the ixgbe TX function to be used into a separate function inside the ixgbe driver, and call that from a secondary process when it is attaching to an already-configured NIC. Testing with symmetric MP app shows that we are able to RX and TX from both primary and secondary processes once this patch is applied. Signed-off-by: Bruce Richardson <bruce.richardson@intel.com> Acked-by: Reshma Pattan <reshma.pattan@intel.com>
271 lines
10 KiB
C
271 lines
10 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _IXGBE_RXTX_H_
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#define _IXGBE_RXTX_H_
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#define RTE_PMD_IXGBE_TX_MAX_BURST 32
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#ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
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#define RTE_PMD_IXGBE_RX_MAX_BURST 32
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#define RTE_IXGBE_DESCS_PER_LOOP 4
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#elif defined(RTE_IXGBE_INC_VECTOR)
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#define RTE_IXGBE_DESCS_PER_LOOP 4
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#else
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#define RTE_IXGBE_DESCS_PER_LOOP 1
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#endif
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#define RTE_MBUF_DATA_DMA_ADDR(mb) \
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(uint64_t) ((mb)->buf_physaddr + (mb)->data_off)
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#define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
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(uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
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#ifdef RTE_IXGBE_INC_VECTOR
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#define RTE_IXGBE_VPMD_RX_BURST 32
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#define RTE_IXGBE_VPMD_TX_BURST 32
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#define RTE_IXGBE_RXQ_REARM_THRESH RTE_IXGBE_VPMD_RX_BURST
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#define RTE_IXGBE_TX_MAX_FREE_BUF_SZ 64
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#endif
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#define RX_RING_SZ ((IXGBE_MAX_RING_DESC + RTE_IXGBE_DESCS_PER_LOOP - 1) * \
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sizeof(union ixgbe_adv_rx_desc))
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#ifdef RTE_PMD_PACKET_PREFETCH
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#define rte_packet_prefetch(p) rte_prefetch1(p)
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#else
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#define rte_packet_prefetch(p) do {} while(0)
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#endif
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#define RTE_IXGBE_REGISTER_POLL_WAIT_10_MS 10
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#define RTE_IXGBE_WAIT_100_US 100
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#define RTE_IXGBE_VMTXSW_REGISTER_COUNT 2
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/**
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* Structure associated with each descriptor of the RX ring of a RX queue.
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*/
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struct igb_rx_entry {
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struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
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};
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/**
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* Structure associated with each descriptor of the TX ring of a TX queue.
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*/
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struct igb_tx_entry {
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struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
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uint16_t next_id; /**< Index of next descriptor in ring. */
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uint16_t last_id; /**< Index of last scattered descriptor. */
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};
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/**
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* Structure associated with each descriptor of the TX ring of a TX queue.
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*/
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struct igb_tx_entry_v {
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struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
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};
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/**
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* Structure associated with each RX queue.
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*/
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struct igb_rx_queue {
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struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
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volatile union ixgbe_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
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uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
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volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
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volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
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struct igb_rx_entry *sw_ring; /**< address of RX software ring. */
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struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
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struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
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uint64_t mbuf_initializer; /**< value to init mbufs */
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uint16_t nb_rx_desc; /**< number of RX descriptors. */
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uint16_t rx_tail; /**< current value of RDT register. */
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uint16_t nb_rx_hold; /**< number of held free RX desc. */
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#ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
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uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */
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uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */
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uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
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#endif
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#ifdef RTE_IXGBE_INC_VECTOR
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uint16_t rxrearm_nb; /**< the idx we start the re-arming from */
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uint16_t rxrearm_start; /**< number of remaining to be re-armed */
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#endif
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uint16_t rx_free_thresh; /**< max free RX desc to hold. */
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uint16_t queue_id; /**< RX queue index. */
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uint16_t reg_idx; /**< RX queue register index. */
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uint8_t port_id; /**< Device port identifier. */
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uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
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uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
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uint8_t rx_deferred_start; /**< not in global dev start. */
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#ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
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/** need to alloc dummy mbuf, for wraparound when scanning hw ring */
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struct rte_mbuf fake_mbuf;
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/** hold packets to return to application */
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struct rte_mbuf *rx_stage[RTE_PMD_IXGBE_RX_MAX_BURST*2];
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#endif
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};
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/**
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* IXGBE CTX Constants
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*/
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enum ixgbe_advctx_num {
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IXGBE_CTX_0 = 0, /**< CTX0 */
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IXGBE_CTX_1 = 1, /**< CTX1 */
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IXGBE_CTX_NUM = 2, /**< CTX NUMBER */
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};
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/** Offload features */
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union ixgbe_tx_offload {
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uint64_t data;
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struct {
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uint64_t l2_len:7; /**< L2 (MAC) Header Length. */
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uint64_t l3_len:9; /**< L3 (IP) Header Length. */
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uint64_t l4_len:8; /**< L4 (TCP/UDP) Header Length. */
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uint64_t tso_segsz:16; /**< TCP TSO segment size */
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uint64_t vlan_tci:16;
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/**< VLAN Tag Control Identifier (CPU order). */
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};
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};
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/*
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* Compare mask for vlan_macip_len.data,
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* should be in sync with ixgbe_vlan_macip.f layout.
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* */
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#define TX_VLAN_CMP_MASK 0xFFFF0000 /**< VLAN length - 16-bits. */
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#define TX_MAC_LEN_CMP_MASK 0x0000FE00 /**< MAC length - 7-bits. */
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#define TX_IP_LEN_CMP_MASK 0x000001FF /**< IP length - 9-bits. */
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/** MAC+IP length. */
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#define TX_MACIP_LEN_CMP_MASK (TX_MAC_LEN_CMP_MASK | TX_IP_LEN_CMP_MASK)
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/**
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* Structure to check if new context need be built
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*/
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struct ixgbe_advctx_info {
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uint64_t flags; /**< ol_flags for context build. */
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/**< tx offload: vlan, tso, l2-l3-l4 lengths. */
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union ixgbe_tx_offload tx_offload;
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/** compare mask for tx offload. */
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union ixgbe_tx_offload tx_offload_mask;
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};
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/**
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* Structure associated with each TX queue.
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*/
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struct igb_tx_queue {
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/** TX ring virtual address. */
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volatile union ixgbe_adv_tx_desc *tx_ring;
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uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
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struct igb_tx_entry *sw_ring; /**< virtual address of SW ring. */
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volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
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uint16_t nb_tx_desc; /**< number of TX descriptors. */
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uint16_t tx_tail; /**< current value of TDT reg. */
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uint16_t tx_free_thresh;/**< minimum TX before freeing. */
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/** Number of TX descriptors to use before RS bit is set. */
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uint16_t tx_rs_thresh;
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/** Number of TX descriptors used since RS bit was set. */
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uint16_t nb_tx_used;
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/** Index to last TX descriptor to have been cleaned. */
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uint16_t last_desc_cleaned;
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/** Total number of TX descriptors ready to be allocated. */
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uint16_t nb_tx_free;
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uint16_t tx_next_dd; /**< next desc to scan for DD bit */
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uint16_t tx_next_rs; /**< next desc to set RS bit */
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uint16_t queue_id; /**< TX queue index. */
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uint16_t reg_idx; /**< TX queue register index. */
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uint8_t port_id; /**< Device port identifier. */
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uint8_t pthresh; /**< Prefetch threshold register. */
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uint8_t hthresh; /**< Host threshold register. */
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uint8_t wthresh; /**< Write-back threshold reg. */
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uint32_t txq_flags; /**< Holds flags for this TXq */
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uint32_t ctx_curr; /**< Hardware context states. */
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/** Hardware context0 history. */
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struct ixgbe_advctx_info ctx_cache[IXGBE_CTX_NUM];
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struct ixgbe_txq_ops *ops; /**< txq ops */
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uint8_t tx_deferred_start; /**< not in global dev start. */
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};
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struct ixgbe_txq_ops {
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void (*release_mbufs)(struct igb_tx_queue *txq);
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void (*free_swring)(struct igb_tx_queue *txq);
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void (*reset)(struct igb_tx_queue *txq);
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};
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/*
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* The "simple" TX queue functions require that the following
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* flags are set when the TX queue is configured:
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* - ETH_TXQ_FLAGS_NOMULTSEGS
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* - ETH_TXQ_FLAGS_NOVLANOFFL
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* - ETH_TXQ_FLAGS_NOXSUMSCTP
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* - ETH_TXQ_FLAGS_NOXSUMUDP
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* - ETH_TXQ_FLAGS_NOXSUMTCP
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* and that the RS bit threshold (tx_rs_thresh) is at least equal to
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* RTE_PMD_IXGBE_TX_MAX_BURST.
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*/
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#define IXGBE_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
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ETH_TXQ_FLAGS_NOOFFLOADS)
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/*
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* Populate descriptors with the following info:
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* 1.) buffer_addr = phys_addr + headroom
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* 2.) cmd_type_len = DCMD_DTYP_FLAGS | pkt_len
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* 3.) olinfo_status = pkt_len << PAYLEN_SHIFT
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*/
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/* Defines for Tx descriptor */
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#define DCMD_DTYP_FLAGS (IXGBE_ADVTXD_DTYP_DATA |\
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IXGBE_ADVTXD_DCMD_IFCS |\
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IXGBE_ADVTXD_DCMD_DEXT |\
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IXGBE_ADVTXD_DCMD_EOP)
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/* Takes an ethdev and a queue and sets up the tx function to be used based on
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* the queue parameters. Used in tx_queue_setup by primary process and then
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* in dev_init by secondary process when attaching to an existing ethdev.
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*/
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void set_tx_function(struct rte_eth_dev *dev, struct igb_tx_queue *txq);
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#ifdef RTE_IXGBE_INC_VECTOR
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uint16_t ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t ixgbe_recv_scattered_pkts_vec(void *rx_queue,
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struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
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uint16_t ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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int ixgbe_txq_vec_setup(struct igb_tx_queue *txq);
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int ixgbe_rxq_vec_setup(struct igb_rx_queue *rxq);
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int ixgbe_rx_vec_condition_check(struct rte_eth_dev *dev);
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#endif
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#endif
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