dd93390e57
This patch deletes ceq interfaces that not needed, fix aeq buges in some scenarios. Signed-off-by: Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>
136 lines
4.2 KiB
C
136 lines
4.2 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2017 Huawei Technologies Co., Ltd
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*/
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#ifndef _HINIC_CSR_H_
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#define _HINIC_CSR_H_
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#define HINIC_CSR_GLOBAL_BASE_ADDR 0x4000
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/* HW interface registers */
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#define HINIC_CSR_FUNC_ATTR0_ADDR 0x0
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#define HINIC_CSR_FUNC_ATTR1_ADDR 0x4
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#define HINIC_CSR_FUNC_ATTR2_ADDR 0x8
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#define HINIC_CSR_FUNC_ATTR4_ADDR 0x10
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#define HINIC_CSR_FUNC_ATTR5_ADDR 0x14
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#define HINIC_FUNC_CSR_MAILBOX_DATA_OFF 0x80
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#define HINIC_FUNC_CSR_MAILBOX_CONTROL_OFF 0x0100
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#define HINIC_FUNC_CSR_MAILBOX_INT_OFFSET_OFF 0x0104
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#define HINIC_FUNC_CSR_MAILBOX_RESULT_H_OFF 0x0108
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#define HINIC_FUNC_CSR_MAILBOX_RESULT_L_OFF 0x010C
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#define HINIC_CSR_DMA_ATTR_TBL_BASE 0xC80
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#define HINIC_ELECTION_BASE 0x200
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#define HINIC_CSR_DMA_ATTR_TBL_STRIDE 0x4
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#define HINIC_CSR_DMA_ATTR_TBL_ADDR(idx) \
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(HINIC_CSR_DMA_ATTR_TBL_BASE \
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+ (idx) * HINIC_CSR_DMA_ATTR_TBL_STRIDE)
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#define HINIC_PPF_ELECTION_STRIDE 0x4
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#define HINIC_CSR_MAX_PORTS 4
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#define HINIC_CSR_PPF_ELECTION_ADDR \
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(HINIC_CSR_GLOBAL_BASE_ADDR + HINIC_ELECTION_BASE)
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/* MSI-X registers */
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#define HINIC_CSR_MSIX_CTRL_BASE 0x2000
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#define HINIC_CSR_MSIX_CNT_BASE 0x2004
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#define HINIC_CSR_MSIX_STRIDE 0x8
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#define HINIC_CSR_MSIX_CTRL_ADDR(idx) \
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(HINIC_CSR_MSIX_CTRL_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)
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#define HINIC_CSR_MSIX_CNT_ADDR(idx) \
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(HINIC_CSR_MSIX_CNT_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)
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/* EQ registers */
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#define HINIC_AEQ_MTT_OFF_BASE_ADDR 0x200
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#define HINIC_EQ_MTT_OFF_STRIDE 0x40
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#define HINIC_CSR_AEQ_MTT_OFF(id) \
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(HINIC_AEQ_MTT_OFF_BASE_ADDR + (id) * HINIC_EQ_MTT_OFF_STRIDE)
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#define HINIC_CSR_EQ_PAGE_OFF_STRIDE 8
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#define HINIC_AEQ_HI_PHYS_ADDR_REG(q_id, pg_num) \
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(HINIC_CSR_AEQ_MTT_OFF(q_id) + \
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(pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE)
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#define HINIC_AEQ_LO_PHYS_ADDR_REG(q_id, pg_num) \
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(HINIC_CSR_AEQ_MTT_OFF(q_id) + \
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(pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE + 4)
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#define HINIC_EQ_HI_PHYS_ADDR_REG(type, q_id, pg_num) \
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((u32)(HINIC_AEQ_HI_PHYS_ADDR_REG(q_id, pg_num)))
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#define HINIC_EQ_LO_PHYS_ADDR_REG(type, q_id, pg_num) \
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((u32)(HINIC_AEQ_LO_PHYS_ADDR_REG(q_id, pg_num)))
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#define HINIC_AEQ_CTRL_0_ADDR_BASE 0xE00
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#define HINIC_AEQ_CTRL_1_ADDR_BASE 0xE04
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#define HINIC_AEQ_CONS_IDX_0_ADDR_BASE 0xE08
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#define HINIC_AEQ_CONS_IDX_1_ADDR_BASE 0xE0C
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#define HINIC_EQ_OFF_STRIDE 0x80
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#define HINIC_CSR_AEQ_CTRL_0_ADDR(idx) \
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(HINIC_AEQ_CTRL_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
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#define HINIC_CSR_AEQ_CTRL_1_ADDR(idx) \
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(HINIC_AEQ_CTRL_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
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#define HINIC_CSR_AEQ_CONS_IDX_ADDR(idx) \
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(HINIC_AEQ_CONS_IDX_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
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#define HINIC_CSR_AEQ_PROD_IDX_ADDR(idx) \
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(HINIC_AEQ_CONS_IDX_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
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/* API CMD registers */
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#define HINIC_CSR_API_CMD_BASE 0xF000
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#define HINIC_CSR_API_CMD_STRIDE 0x100
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#define HINIC_CSR_API_CMD_CHAIN_HEAD_HI_ADDR(idx) \
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(HINIC_CSR_API_CMD_BASE + 0x0 + (idx) * HINIC_CSR_API_CMD_STRIDE)
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#define HINIC_CSR_API_CMD_CHAIN_HEAD_LO_ADDR(idx) \
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(HINIC_CSR_API_CMD_BASE + 0x4 + (idx) * HINIC_CSR_API_CMD_STRIDE)
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#define HINIC_CSR_API_CMD_STATUS_HI_ADDR(idx) \
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(HINIC_CSR_API_CMD_BASE + 0x8 + (idx) * HINIC_CSR_API_CMD_STRIDE)
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#define HINIC_CSR_API_CMD_STATUS_LO_ADDR(idx) \
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(HINIC_CSR_API_CMD_BASE + 0xC + (idx) * HINIC_CSR_API_CMD_STRIDE)
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#define HINIC_CSR_API_CMD_CHAIN_NUM_CELLS_ADDR(idx) \
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(HINIC_CSR_API_CMD_BASE + 0x10 + (idx) * HINIC_CSR_API_CMD_STRIDE)
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#define HINIC_CSR_API_CMD_CHAIN_CTRL_ADDR(idx) \
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(HINIC_CSR_API_CMD_BASE + 0x14 + (idx) * HINIC_CSR_API_CMD_STRIDE)
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#define HINIC_CSR_API_CMD_CHAIN_PI_ADDR(idx) \
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(HINIC_CSR_API_CMD_BASE + 0x1C + (idx) * HINIC_CSR_API_CMD_STRIDE)
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#define HINIC_CSR_API_CMD_CHAIN_REQ_ADDR(idx) \
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(HINIC_CSR_API_CMD_BASE + 0x20 + (idx) * HINIC_CSR_API_CMD_STRIDE)
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#define HINIC_CSR_API_CMD_STATUS_0_ADDR(idx) \
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(HINIC_CSR_API_CMD_BASE + 0x30 + (idx) * HINIC_CSR_API_CMD_STRIDE)
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/* VF control registers in pf */
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#define HINIC_PF_CSR_VF_FLUSH_BASE 0x1F400
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#define HINIC_PF_CSR_VF_FLUSH_STRIDE 0x4
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#define HINIC_GLB_DMA_SO_RO_REPLACE_ADDR 0x488C
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#define HINIC_ICPL_RESERVD_ADDR 0x9204
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#define HINIC_PF_CSR_VF_FLUSH_OFF(idx) \
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(HINIC_PF_CSR_VF_FLUSH_BASE + (idx) * HINIC_PF_CSR_VF_FLUSH_STRIDE)
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#endif /* _HINIC_CSR_H_ */
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