d9ce191794
Add code for hardware operation, including configuration, query and so on. Signed-off-by: Ziyang Xuan <xuanziyang2@huawei.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
146 lines
3.1 KiB
C
146 lines
3.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2017 Huawei Technologies Co., Ltd
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*/
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#ifndef _HINIC_PMD_CFG_H_
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#define _HINIC_PMD_CFG_H_
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#define CFG_MAX_CMD_TIMEOUT 8000 /* ms */
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#define IS_NIC_TYPE(dev) \
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((dev)->cfg_mgmt->svc_cap.chip_svc_type & CFG_SVC_NIC_BIT0)
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struct host_shared_resource_cap {
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u32 host_pctxs; /* Parent Context max 1M, IOE and FCoE max 8K flows */
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u32 host_cctxs; /* Child Context: max 8K */
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u32 host_scqs; /* shared CQ, chip interface module uses 1 SCQ
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* TOE/IOE/FCoE each uses 1 SCQ
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* RoCE/IWARP uses multiple SCQs
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* So 6 SCQ least
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*/
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u32 host_srqs; /* SRQ number: 256K */
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u32 host_mpts; /* MR number:1M */
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};
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struct nic_service_cap {
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/* PF resources */
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u16 max_sqs;
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u16 max_rqs;
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/* VF resources, VF obtain them through the MailBox mechanism from
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* corresponding PF
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*/
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u16 vf_max_sqs;
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u16 vf_max_rqs;
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bool lro_en; /* LRO feature enable bit */
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u8 lro_sz; /* LRO context space: n*16B */
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u8 tso_sz; /* TSO context space: n*16B */
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};
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/* service type relates define */
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enum cfg_svc_type_en {
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CFG_SVC_NIC_BIT0 = (1 << 0),
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};
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/* device capability */
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struct service_cap {
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enum cfg_svc_type_en chip_svc_type; /* HW supported service type */
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/* Host global resources */
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u16 host_total_function;
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u8 host_oq_id_mask_val;
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u8 host_id;
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u8 ep_id;
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u8 intr_chip_en;
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u8 max_cos_id; /* PF/VF's max cos id */
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u8 er_id; /* PF/VF's ER */
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u8 port_id; /* PF/VF's physical port */
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u8 max_vf; /* max VF number that PF supported */
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bool sf_en; /* stateful business status */
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u16 max_sqs;
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u16 max_rqs;
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u32 pf_num;
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u32 pf_id_start;
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u32 vf_num;
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u32 vf_id_start;
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struct host_shared_resource_cap shared_res_cap; /* shared capability */
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struct nic_service_cap nic_cap; /* NIC capability */
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};
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struct cfg_mgmt_info {
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struct hinic_hwdev *hwdev;
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struct service_cap svc_cap;
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};
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struct hinic_dev_cap {
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struct hinic_mgmt_msg_head mgmt_msg_head;
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/* Public resource */
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u8 sf_svc_attr;
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u8 host_id;
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u8 sf_en_pf;
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u8 sf_en_vf;
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u8 ep_id;
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u8 intr_type;
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u8 max_cos_id;
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u8 er_id;
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u8 port_id;
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u8 max_vf;
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u16 svc_cap_en;
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u16 host_total_func;
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u8 host_oq_id_mask_val;
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u8 max_vf_cos_id;
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u32 max_conn_num;
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u16 max_stick2cache_num;
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u16 max_bfilter_start_addr;
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u16 bfilter_len;
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u16 hash_bucket_num;
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u8 cfg_file_ver;
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u8 net_port_mode;
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u8 valid_cos_bitmap; /* every bit indicate cos is valid */
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u8 rsvd1;
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u32 pf_num;
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u32 pf_id_start;
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u32 vf_num;
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u32 vf_id_start;
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/* shared resource */
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u32 host_pctx_num;
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u8 host_sf_en;
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u8 rsvd2[3];
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u32 host_ccxt_num;
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u32 host_scq_num;
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u32 host_srq_num;
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u32 host_mpt_num;
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/* l2nic */
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u16 nic_max_sq;
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u16 nic_max_rq;
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u16 nic_vf_max_sq;
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u16 nic_vf_max_rq;
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u8 nic_lro_en;
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u8 nic_lro_sz;
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u8 nic_tso_sz;
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u8 rsvd3;
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u32 rsvd4[50];
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};
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/* Obtain service_cap.nic_cap.dev_nic_cap.max_sqs */
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u16 hinic_func_max_qnum(void *hwdev);
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int init_cfg_mgmt(struct hinic_hwdev *hwdev);
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void free_cfg_mgmt(struct hinic_hwdev *hwdev);
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int hinic_init_capability(struct hinic_hwdev *hwdev);
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bool hinic_support_nic(struct hinic_hwdev *hwdev, struct nic_service_cap *cap);
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#endif /* _HINIC_PMD_CFG_H_ */
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