0023e525a5
When the filter rule needs to use the TCAM method, driver
enables the TCAM filter switch, otherwise disables it, which
can improve the performance of microcode in FDIR scenarios that
does not use TCAM method.
Fixes: 1fe89aa37f ("net/hinic: add flow director filter")
Cc: stable@dpdk.org
Signed-off-by: Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>
471 lines
12 KiB
C
471 lines
12 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2017 Huawei Technologies Co., Ltd
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*/
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#ifndef _HINIC_PORT_CMD_H_
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#define _HINIC_PORT_CMD_H_
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#define HINIC_AEQ 0
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enum hinic_resp_aeq_num {
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HINIC_AEQ0 = 0,
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HINIC_AEQ1 = 1,
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HINIC_AEQ2 = 2,
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HINIC_AEQ3 = 3,
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};
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enum hinic_mod_type {
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HINIC_MOD_COMM = 0, /* HW communication module */
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HINIC_MOD_L2NIC = 1, /* L2NIC module */
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HINIC_MOD_CFGM = 7, /* Configuration module */
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HINIC_MOD_HILINK = 14,
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HINIC_MOD_MAX = 15
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};
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/* only used by VFD communicating with PFD to register or unregister,
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* command mode type is HINIC_MOD_L2NIC
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*/
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#define HINIC_PORT_CMD_VF_REGISTER 0x0
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#define HINIC_PORT_CMD_VF_UNREGISTER 0x1
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/* cmd of mgmt CPU message for NIC module */
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enum hinic_port_cmd {
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HINIC_PORT_CMD_MGMT_RESET = 0x0,
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HINIC_PORT_CMD_CHANGE_MTU = 0x2,
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HINIC_PORT_CMD_ADD_VLAN = 0x3,
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HINIC_PORT_CMD_DEL_VLAN,
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HINIC_PORT_CMD_SET_ETS = 0x7,
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HINIC_PORT_CMD_GET_ETS,
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HINIC_PORT_CMD_SET_MAC = 0x9,
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HINIC_PORT_CMD_GET_MAC,
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HINIC_PORT_CMD_DEL_MAC,
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HINIC_PORT_CMD_SET_RX_MODE = 0xc,
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HINIC_PORT_CMD_SET_ANTI_ATTACK_RATE = 0xd,
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HINIC_PORT_CMD_GET_PAUSE_INFO = 0x14,
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HINIC_PORT_CMD_SET_PAUSE_INFO,
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HINIC_PORT_CMD_GET_LINK_STATE = 0x18,
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HINIC_PORT_CMD_SET_LRO = 0x19,
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HINIC_PORT_CMD_SET_RX_CSUM = 0x1a,
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HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD = 0x1b,
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HINIC_PORT_CMD_GET_PORT_STATISTICS = 0x1c,
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HINIC_PORT_CMD_CLEAR_PORT_STATISTICS,
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HINIC_PORT_CMD_GET_VPORT_STAT,
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HINIC_PORT_CMD_CLEAN_VPORT_STAT,
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HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 0x25,
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HINIC_PORT_CMD_SET_RSS_TEMPLATE_INDIR_TBL,
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HINIC_PORT_CMD_SET_PORT_ENABLE = 0x29,
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HINIC_PORT_CMD_GET_PORT_ENABLE,
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HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL = 0x2b,
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HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL,
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HINIC_PORT_CMD_SET_RSS_HASH_ENGINE,
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HINIC_PORT_CMD_GET_RSS_HASH_ENGINE,
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HINIC_PORT_CMD_GET_RSS_CTX_TBL,
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HINIC_PORT_CMD_SET_RSS_CTX_TBL,
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HINIC_PORT_CMD_RSS_TEMP_MGR,
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HINIC_PORT_CMD_RSS_CFG = 0x42,
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HINIC_PORT_CMD_GET_PHY_TYPE = 0x44,
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HINIC_PORT_CMD_INIT_FUNC = 0x45,
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HINIC_PORT_CMD_GET_JUMBO_FRAME_SIZE = 0x4a,
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HINIC_PORT_CMD_SET_JUMBO_FRAME_SIZE,
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HINIC_PORT_CMD_GET_MGMT_VERSION = 0x58,
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HINIC_PORT_CMD_GET_PORT_TYPE = 0x5b,
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HINIC_PORT_CMD_GET_VPORT_ENABLE = 0x5c,
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HINIC_PORT_CMD_SET_VPORT_ENABLE,
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HINIC_PORT_CMD_GET_PORT_ID_BY_FUNC_ID = 0x5e,
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HINIC_PORT_CMD_GET_LRO = 0x63,
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HINIC_PORT_CMD_GET_DMA_CS = 0x64,
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HINIC_PORT_CMD_SET_DMA_CS,
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HINIC_PORT_CMD_GET_GLOBAL_QPN = 0x66,
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HINIC_PORT_CMD_SET_PFC_MISC = 0x67,
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HINIC_PORT_CMD_GET_PFC_MISC,
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HINIC_PORT_CMD_SET_VF_RATE = 0x69,
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HINIC_PORT_CMD_SET_VF_VLAN,
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HINIC_PORT_CMD_CLR_VF_VLAN,
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HINIC_PORT_CMD_SET_RQ_IQ_MAP = 0x73,
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HINIC_PORT_CMD_SET_PFC_THD = 0x75,
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HINIC_PORT_CMD_LINK_STATUS_REPORT = 0xa0,
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HINIC_PORT_CMD_SET_LOSSLESS_ETH = 0xa3,
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HINIC_PORT_CMD_UPDATE_MAC = 0xa4,
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HINIC_PORT_CMD_GET_PORT_INFO = 0xaa,
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HINIC_PORT_CMD_UP_TC_ADD_FLOW = 0xaf,
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HINIC_PORT_CMD_UP_TC_DEL_FLOW = 0xb0,
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HINIC_PORT_CMD_UP_TC_GET_FLOW = 0xb1,
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HINIC_PORT_CMD_UP_TC_FLUSH_TCAM = 0xb2,
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HINIC_PORT_CMD_UP_TC_CTRL_TCAM_BLOCK = 0xb3,
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HINIC_PORT_CMD_UP_TC_ENABLE = 0xb4,
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HINIC_PORT_CMD_SET_IPSU_MAC = 0xcb,
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HINIC_PORT_CMD_GET_IPSU_MAC = 0xcc,
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HINIC_PORT_CMD_SET_XSFP_STATUS = 0xD4,
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HINIC_PORT_CMD_GET_LINK_MODE = 0xD9,
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HINIC_PORT_CMD_SET_SPEED = 0xDA,
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HINIC_PORT_CMD_SET_AUTONEG = 0xDB,
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HINIC_PORT_CMD_CLEAR_QP_RES = 0xDD,
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HINIC_PORT_CMD_SET_SUPER_CQE = 0xDE,
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HINIC_PORT_CMD_SET_VF_COS = 0xDF,
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HINIC_PORT_CMD_GET_VF_COS = 0xE1,
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HINIC_PORT_CMD_CABLE_PLUG_EVENT = 0xE5,
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HINIC_PORT_CMD_LINK_ERR_EVENT = 0xE6,
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HINIC_PORT_CMD_SET_COS_UP_MAP = 0xE8,
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HINIC_PORT_CMD_RESET_LINK_CFG = 0xEB,
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HINIC_PORT_CMD_FORCE_PKT_DROP = 0xF3,
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HINIC_PORT_CMD_SET_LRO_TIMER = 0xF4,
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HINIC_PORT_CMD_SET_VHD_CFG = 0xF7,
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HINIC_PORT_CMD_SET_LINK_FOLLOW = 0xF8,
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HINIC_PORT_CMD_Q_FILTER = 0xFC,
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HINIC_PORT_CMD_TCAM_FILTER = 0xFE,
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HINIC_PORT_CMD_SET_VLAN_FILTER = 0xFF
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};
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/* cmd of mgmt CPU message for HW module */
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enum hinic_mgmt_cmd {
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HINIC_MGMT_CMD_RESET_MGMT = 0x0,
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HINIC_MGMT_CMD_START_FLR = 0x1,
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HINIC_MGMT_CMD_FLUSH_DOORBELL = 0x2,
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HINIC_MGMT_CMD_GET_IO_STATUS = 0x3,
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HINIC_MGMT_CMD_DMA_ATTR_SET = 0x4,
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HINIC_MGMT_CMD_CMDQ_CTXT_SET = 0x10,
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HINIC_MGMT_CMD_CMDQ_CTXT_GET,
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HINIC_MGMT_CMD_VAT_SET = 0x12,
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HINIC_MGMT_CMD_VAT_GET,
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HINIC_MGMT_CMD_L2NIC_SQ_CI_ATTR_SET = 0x14,
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HINIC_MGMT_CMD_L2NIC_SQ_CI_ATTR_GET,
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HINIC_MGMT_CMD_PPF_HT_GPA_SET = 0x23,
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HINIC_MGMT_CMD_RES_STATE_SET = 0x24,
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HINIC_MGMT_CMD_FUNC_CACHE_OUT = 0x25,
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HINIC_MGMT_CMD_FFM_SET = 0x26,
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HINIC_MGMT_CMD_FUNC_RES_CLEAR = 0x29,
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HINIC_MGMT_CMD_CEQ_CTRL_REG_WR_BY_UP = 0x33,
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HINIC_MGMT_CMD_MSI_CTRL_REG_WR_BY_UP,
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HINIC_MGMT_CMD_MSI_CTRL_REG_RD_BY_UP,
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HINIC_MGMT_CMD_VF_RANDOM_ID_SET = 0x36,
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HINIC_MGMT_CMD_FAULT_REPORT = 0x37,
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HINIC_MGMT_CMD_VPD_SET = 0x40,
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HINIC_MGMT_CMD_VPD_GET,
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HINIC_MGMT_CMD_LABEL_SET,
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HINIC_MGMT_CMD_LABEL_GET,
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HINIC_MGMT_CMD_SATIC_MAC_SET,
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HINIC_MGMT_CMD_SATIC_MAC_GET,
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HINIC_MGMT_CMD_SYNC_TIME = 0x46,
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HINIC_MGMT_CMD_SET_LED_STATUS = 0x4A,
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HINIC_MGMT_CMD_L2NIC_RESET = 0x4b,
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HINIC_MGMT_CMD_FAST_RECYCLE_MODE_SET = 0x4d,
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HINIC_MGMT_CMD_BIOS_NV_DATA_MGMT = 0x4E,
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HINIC_MGMT_CMD_ACTIVATE_FW = 0x4F,
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HINIC_MGMT_CMD_PAGESIZE_SET = 0x50,
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HINIC_MGMT_CMD_PAGESIZE_GET = 0x51,
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HINIC_MGMT_CMD_GET_BOARD_INFO = 0x52,
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HINIC_MGMT_CMD_WATCHDOG_INFO = 0x56,
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HINIC_MGMT_CMD_FMW_ACT_NTC = 0x57,
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HINIC_MGMT_CMD_SET_VF_RANDOM_ID = 0x61,
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HINIC_MGMT_CMD_GET_PPF_STATE = 0x63,
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HINIC_MGMT_CMD_PCIE_DFX_NTC = 0x65,
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HINIC_MGMT_CMD_PCIE_DFX_GET = 0x66,
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};
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/* cmd of mgmt CPU message for HILINK module */
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enum hinic_hilink_cmd {
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HINIC_HILINK_CMD_GET_LINK_INFO = 0x3,
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HINIC_HILINK_CMD_SET_LINK_SETTINGS = 0x8,
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};
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/* uCode related commands */
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enum hinic_ucode_cmd {
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HINIC_UCODE_CMD_MDY_QUEUE_CONTEXT = 0,
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HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT,
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HINIC_UCODE_CMD_ARM_SQ,
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HINIC_UCODE_CMD_ARM_RQ,
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HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE,
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HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE,
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HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE,
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HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE,
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HINIC_UCODE_CMD_SET_IQ_ENABLE,
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HINIC_UCODE_CMD_SET_RQ_FLUSH = 10
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};
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enum cfg_sub_cmd {
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/* PPF(PF) <-> FW */
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HINIC_CFG_NIC_CAP = 0,
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CFG_FW_VERSION,
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CFG_UCODE_VERSION,
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HINIC_CFG_MBOX_CAP = 6
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};
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enum hinic_ack_type {
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HINIC_ACK_TYPE_CMDQ,
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HINIC_ACK_TYPE_SHARE_CQN,
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HINIC_ACK_TYPE_APP_CQN,
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HINIC_MOD_ACK_MAX = 15,
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};
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enum sq_l4offload_type {
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OFFLOAD_DISABLE = 0,
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TCP_OFFLOAD_ENABLE = 1,
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SCTP_OFFLOAD_ENABLE = 2,
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UDP_OFFLOAD_ENABLE = 3,
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};
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enum sq_vlan_offload_flag {
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VLAN_OFFLOAD_DISABLE = 0,
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VLAN_OFFLOAD_ENABLE = 1,
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};
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enum sq_pkt_parsed_flag {
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PKT_NOT_PARSED = 0,
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PKT_PARSED = 1,
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};
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enum sq_l3_type {
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UNKNOWN_L3TYPE = 0,
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IPV6_PKT = 1,
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IPV4_PKT_NO_CHKSUM_OFFLOAD = 2,
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IPV4_PKT_WITH_CHKSUM_OFFLOAD = 3,
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};
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enum sq_md_type {
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UNKNOWN_MD_TYPE = 0,
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};
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enum sq_l2type {
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ETHERNET = 0,
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};
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enum sq_tunnel_l4_type {
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NOT_TUNNEL,
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TUNNEL_UDP_NO_CSUM,
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TUNNEL_UDP_CSUM,
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};
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#define NIC_RSS_CMD_TEMP_ALLOC 0x01
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#define NIC_RSS_CMD_TEMP_FREE 0x02
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#define HINIC_RSS_TYPE_VALID_SHIFT 23
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#define HINIC_RSS_TYPE_TCP_IPV6_EXT_SHIFT 24
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#define HINIC_RSS_TYPE_IPV6_EXT_SHIFT 25
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#define HINIC_RSS_TYPE_TCP_IPV6_SHIFT 26
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#define HINIC_RSS_TYPE_IPV6_SHIFT 27
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#define HINIC_RSS_TYPE_TCP_IPV4_SHIFT 28
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#define HINIC_RSS_TYPE_IPV4_SHIFT 29
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#define HINIC_RSS_TYPE_UDP_IPV6_SHIFT 30
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#define HINIC_RSS_TYPE_UDP_IPV4_SHIFT 31
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#define HINIC_RSS_TYPE_SET(val, member) \
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(((u32)(val) & 0x1) << HINIC_RSS_TYPE_##member##_SHIFT)
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#define HINIC_RSS_TYPE_GET(val, member) \
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(((u32)(val) >> HINIC_RSS_TYPE_##member##_SHIFT) & 0x1)
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enum hinic_speed {
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HINIC_SPEED_10MB_LINK = 0,
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HINIC_SPEED_100MB_LINK,
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HINIC_SPEED_1000MB_LINK,
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HINIC_SPEED_10GB_LINK,
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HINIC_SPEED_25GB_LINK,
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HINIC_SPEED_40GB_LINK,
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HINIC_SPEED_100GB_LINK,
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HINIC_SPEED_UNKNOWN = 0xFF,
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};
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enum {
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HINIC_IFLA_VF_LINK_STATE_AUTO, /* link state of the uplink */
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HINIC_IFLA_VF_LINK_STATE_ENABLE, /* link always up */
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HINIC_IFLA_VF_LINK_STATE_DISABLE, /* link always down */
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};
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#define HINIC_AF0_FUNC_GLOBAL_IDX_SHIFT 0
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#define HINIC_AF0_P2P_IDX_SHIFT 10
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#define HINIC_AF0_PCI_INTF_IDX_SHIFT 14
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#define HINIC_AF0_VF_IN_PF_SHIFT 16
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#define HINIC_AF0_FUNC_TYPE_SHIFT 24
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#define HINIC_AF0_FUNC_GLOBAL_IDX_MASK 0x3FF
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#define HINIC_AF0_P2P_IDX_MASK 0xF
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#define HINIC_AF0_PCI_INTF_IDX_MASK 0x3
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#define HINIC_AF0_VF_IN_PF_MASK 0xFF
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#define HINIC_AF0_FUNC_TYPE_MASK 0x1
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#define HINIC_AF0_GET(val, member) \
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(((val) >> HINIC_AF0_##member##_SHIFT) & HINIC_AF0_##member##_MASK)
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#define HINIC_AF1_PPF_IDX_SHIFT 0
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#define HINIC_AF1_AEQS_PER_FUNC_SHIFT 8
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#define HINIC_AF1_CEQS_PER_FUNC_SHIFT 12
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#define HINIC_AF1_IRQS_PER_FUNC_SHIFT 20
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#define HINIC_AF1_DMA_ATTR_PER_FUNC_SHIFT 24
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#define HINIC_AF1_MGMT_INIT_STATUS_SHIFT 30
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#define HINIC_AF1_PF_INIT_STATUS_SHIFT 31
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#define HINIC_AF1_PPF_IDX_MASK 0x1F
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#define HINIC_AF1_AEQS_PER_FUNC_MASK 0x3
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#define HINIC_AF1_CEQS_PER_FUNC_MASK 0x7
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#define HINIC_AF1_IRQS_PER_FUNC_MASK 0xF
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#define HINIC_AF1_DMA_ATTR_PER_FUNC_MASK 0x7
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#define HINIC_AF1_MGMT_INIT_STATUS_MASK 0x1
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#define HINIC_AF1_PF_INIT_STATUS_MASK 0x1
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#define HINIC_AF1_GET(val, member) \
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(((val) >> HINIC_AF1_##member##_SHIFT) & HINIC_AF1_##member##_MASK)
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#define HINIC_AF2_GLOBAL_VF_ID_OF_PF_SHIFT 16
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#define HINIC_AF2_GLOBAL_VF_ID_OF_PF_MASK 0x3FF
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#define HINIC_AF2_GET(val, member) \
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(((val) >> HINIC_AF2_##member##_SHIFT) & HINIC_AF2_##member##_MASK)
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#define HINIC_AF4_OUTBOUND_CTRL_SHIFT 0
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#define HINIC_AF4_DOORBELL_CTRL_SHIFT 1
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#define HINIC_AF4_OUTBOUND_CTRL_MASK 0x1
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#define HINIC_AF4_DOORBELL_CTRL_MASK 0x1
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#define HINIC_AF4_GET(val, member) \
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(((val) >> HINIC_AF4_##member##_SHIFT) & HINIC_AF4_##member##_MASK)
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#define HINIC_AF4_SET(val, member) \
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(((val) & HINIC_AF4_##member##_MASK) << HINIC_AF4_##member##_SHIFT)
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#define HINIC_AF4_CLEAR(val, member) \
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((val) & (~(HINIC_AF4_##member##_MASK << \
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HINIC_AF4_##member##_SHIFT)))
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#define HINIC_AF5_PF_STATUS_SHIFT 0
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#define HINIC_AF5_PF_STATUS_MASK 0xFFFF
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#define HINIC_AF5_SET(val, member) \
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(((val) & HINIC_AF5_##member##_MASK) << HINIC_AF5_##member##_SHIFT)
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#define HINIC_AF5_GET(val, member) \
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(((val) >> HINIC_AF5_##member##_SHIFT) & HINIC_AF5_##member##_MASK)
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#define HINIC_AF5_CLEAR(val, member) \
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((val) & (~(HINIC_AF5_##member##_MASK << \
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HINIC_AF5_##member##_SHIFT)))
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#define HINIC_PPF_ELECTION_IDX_SHIFT 0
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#define HINIC_PPF_ELECTION_IDX_MASK 0x1F
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#define HINIC_PPF_ELECTION_SET(val, member) \
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(((val) & HINIC_PPF_ELECTION_##member##_MASK) << \
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HINIC_PPF_ELECTION_##member##_SHIFT)
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#define HINIC_PPF_ELECTION_GET(val, member) \
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(((val) >> HINIC_PPF_ELECTION_##member##_SHIFT) & \
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HINIC_PPF_ELECTION_##member##_MASK)
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#define HINIC_PPF_ELECTION_CLEAR(val, member) \
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((val) & (~(HINIC_PPF_ELECTION_##member##_MASK \
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<< HINIC_PPF_ELECTION_##member##_SHIFT)))
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#define DB_IDX(db, db_base) \
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((u32)(((unsigned long)(db) - (unsigned long)(db_base)) / \
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HINIC_DB_PAGE_SIZE))
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enum hinic_pcie_nosnoop {
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HINIC_PCIE_SNOOP = 0,
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HINIC_PCIE_NO_SNOOP = 1,
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};
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enum hinic_pcie_tph {
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HINIC_PCIE_TPH_DISABLE = 0,
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HINIC_PCIE_TPH_ENABLE = 1,
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};
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enum hinic_outbound_ctrl {
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ENABLE_OUTBOUND = 0x0,
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DISABLE_OUTBOUND = 0x1,
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|
};
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enum hinic_doorbell_ctrl {
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ENABLE_DOORBELL = 0x0,
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DISABLE_DOORBELL = 0x1,
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};
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enum hinic_pf_status {
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HINIC_PF_STATUS_INIT = 0X0,
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HINIC_PF_STATUS_ACTIVE_FLAG = 0x11,
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HINIC_PF_STATUS_FLR_START_FLAG = 0x12,
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|
HINIC_PF_STATUS_FLR_FINISH_FLAG = 0x13,
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|
};
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/* total doorbell or direct wqe size is 512kB, db num: 128, dwqe: 128 */
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|
#define HINIC_DB_DWQE_SIZE 0x00080000
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|
|
|
/* db page size: 4K */
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|
#define HINIC_DB_PAGE_SIZE 0x00001000ULL
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|
|
|
#define HINIC_DB_MAX_AREAS (HINIC_DB_DWQE_SIZE / HINIC_DB_PAGE_SIZE)
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|
|
|
#define HINIC_PCI_MSIX_ENTRY_SIZE 16
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|
#define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL 12
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|
#define HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT 1
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|
|
|
struct hinic_mgmt_msg_head {
|
|
u8 status;
|
|
u8 version;
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|
u8 resp_aeq_num;
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|
u8 rsvd0[5];
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|
};
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|
|
|
struct hinic_root_ctxt {
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|
struct hinic_mgmt_msg_head mgmt_msg_head;
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|
|
|
u16 func_idx;
|
|
u16 rsvd1;
|
|
u8 set_cmdq_depth;
|
|
u8 cmdq_depth;
|
|
u8 lro_en;
|
|
u8 rsvd2;
|
|
u8 ppf_idx;
|
|
u8 rsvd3;
|
|
u16 rq_depth;
|
|
u16 rx_buf_sz;
|
|
u16 sq_depth;
|
|
};
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|
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#endif /* _HINIC_PORT_CMD_H_ */
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