3260064acc
Following commit updated the error codes:
commit 2ae8e130cf
("net/hinic/base: modify returned error values")
In that commit 'ETIME' errors are not used because it is not supported
by FreeBSD, instead in this patch converting relevant error codes to
'ETIMEDOUT'.
Signed-off-by: Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
555 lines
14 KiB
C
555 lines
14 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2017 Huawei Technologies Co., Ltd
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*/
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#include <rte_bus_pci.h>
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#include "hinic_compat.h"
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#include "hinic_csr.h"
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#include "hinic_pmd_hwdev.h"
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#include "hinic_pmd_hwif.h"
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#define HINIC_CFG_REGS_BAR 0
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#define HINIC_INTR_MSI_BAR 2
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#define HINIC_DB_MEM_BAR 4
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#define PAGE_SIZE_4K 0x1000
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#define PAGE_SIZE_64K 0x10000
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#define HINIC_MSIX_CNT_RESEND_TIMER_SHIFT 29
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#define HINIC_MSIX_CNT_RESEND_TIMER_MASK 0x7U
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#define HINIC_MSIX_CNT_SET(val, member) \
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(((val) & HINIC_MSIX_CNT_##member##_MASK) << \
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HINIC_MSIX_CNT_##member##_SHIFT)
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/**
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* hwif_ready - test if the HW initialization passed
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* @hwdev: the pointer to the private hardware device object
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* Return: 0 - success, negative - failure
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*/
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static int hwif_ready(struct hinic_hwdev *hwdev)
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{
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u32 addr, attr0, attr1;
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addr = HINIC_CSR_FUNC_ATTR1_ADDR;
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attr1 = hinic_hwif_read_reg(hwdev->hwif, addr);
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if (!HINIC_AF1_GET(attr1, MGMT_INIT_STATUS))
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return -EBUSY;
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addr = HINIC_CSR_FUNC_ATTR0_ADDR;
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attr0 = hinic_hwif_read_reg(hwdev->hwif, addr);
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if ((HINIC_AF0_GET(attr0, FUNC_TYPE) == TYPE_VF) &&
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!HINIC_AF1_GET(attr1, PF_INIT_STATUS))
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return -EBUSY;
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return 0;
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}
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/**
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* set_hwif_attr - set the attributes as members in hwif
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* @hwif: the hardware interface of a pci function device
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* @attr0: the first attribute that was read from the hw
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* @attr1: the second attribute that was read from the hw
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* @attr2: the third attribute that was read from the hw
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*/
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static void set_hwif_attr(struct hinic_hwif *hwif, u32 attr0, u32 attr1,
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u32 attr2)
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{
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hwif->attr.func_global_idx = HINIC_AF0_GET(attr0, FUNC_GLOBAL_IDX);
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hwif->attr.port_to_port_idx = HINIC_AF0_GET(attr0, P2P_IDX);
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hwif->attr.pci_intf_idx = HINIC_AF0_GET(attr0, PCI_INTF_IDX);
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hwif->attr.vf_in_pf = HINIC_AF0_GET(attr0, VF_IN_PF);
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hwif->attr.func_type = HINIC_AF0_GET(attr0, FUNC_TYPE);
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hwif->attr.ppf_idx = HINIC_AF1_GET(attr1, PPF_IDX);
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hwif->attr.num_aeqs = BIT(HINIC_AF1_GET(attr1, AEQS_PER_FUNC));
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hwif->attr.num_ceqs = BIT(HINIC_AF1_GET(attr1, CEQS_PER_FUNC));
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hwif->attr.num_irqs = BIT(HINIC_AF1_GET(attr1, IRQS_PER_FUNC));
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hwif->attr.num_dma_attr = BIT(HINIC_AF1_GET(attr1, DMA_ATTR_PER_FUNC));
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hwif->attr.global_vf_id_of_pf = HINIC_AF2_GET(attr2,
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GLOBAL_VF_ID_OF_PF);
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}
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/**
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* get_hwif_attr - read and set the attributes as members in hwif
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* @hwif: the hardware interface of a pci function device
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*/
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static void get_hwif_attr(struct hinic_hwif *hwif)
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{
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u32 addr, attr0, attr1, attr2;
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addr = HINIC_CSR_FUNC_ATTR0_ADDR;
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attr0 = hinic_hwif_read_reg(hwif, addr);
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addr = HINIC_CSR_FUNC_ATTR1_ADDR;
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attr1 = hinic_hwif_read_reg(hwif, addr);
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addr = HINIC_CSR_FUNC_ATTR2_ADDR;
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attr2 = hinic_hwif_read_reg(hwif, addr);
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set_hwif_attr(hwif, attr0, attr1, attr2);
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}
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void hinic_set_pf_status(struct hinic_hwif *hwif, enum hinic_pf_status status)
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{
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u32 attr5 = HINIC_AF5_SET(status, PF_STATUS);
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u32 addr = HINIC_CSR_FUNC_ATTR5_ADDR;
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if (hwif->attr.func_type == TYPE_VF) {
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PMD_DRV_LOG(INFO, "VF doesn't support to set attr5");
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return;
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}
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hinic_hwif_write_reg(hwif, addr, attr5);
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}
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enum hinic_pf_status hinic_get_pf_status(struct hinic_hwif *hwif)
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{
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u32 attr5 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR5_ADDR);
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return HINIC_AF5_GET(attr5, PF_STATUS);
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}
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static enum hinic_doorbell_ctrl
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hinic_get_doorbell_ctrl_status(struct hinic_hwif *hwif)
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{
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u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR);
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return HINIC_AF4_GET(attr4, DOORBELL_CTRL);
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}
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static enum hinic_outbound_ctrl
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hinic_get_outbound_ctrl_status(struct hinic_hwif *hwif)
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{
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u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR);
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return HINIC_AF4_GET(attr4, OUTBOUND_CTRL);
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}
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void hinic_enable_doorbell(struct hinic_hwif *hwif)
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{
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u32 addr, attr4;
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addr = HINIC_CSR_FUNC_ATTR4_ADDR;
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attr4 = hinic_hwif_read_reg(hwif, addr);
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attr4 = HINIC_AF4_CLEAR(attr4, DOORBELL_CTRL);
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attr4 |= HINIC_AF4_SET(ENABLE_DOORBELL, DOORBELL_CTRL);
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hinic_hwif_write_reg(hwif, addr, attr4);
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}
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void hinic_disable_doorbell(struct hinic_hwif *hwif)
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{
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u32 addr, attr4;
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addr = HINIC_CSR_FUNC_ATTR4_ADDR;
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attr4 = hinic_hwif_read_reg(hwif, addr);
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attr4 = HINIC_AF4_CLEAR(attr4, DOORBELL_CTRL);
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attr4 |= HINIC_AF4_SET(DISABLE_DOORBELL, DOORBELL_CTRL);
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hinic_hwif_write_reg(hwif, addr, attr4);
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}
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/**
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* set_ppf - try to set hwif as ppf and set the type of hwif in this case
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* @hwif: the hardware interface of a pci function device
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*/
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static void set_ppf(struct hinic_hwif *hwif)
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{
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struct hinic_func_attr *attr = &hwif->attr;
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u32 addr, val, ppf_election;
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/* Read Modify Write */
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addr = HINIC_CSR_PPF_ELECTION_ADDR;
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val = hinic_hwif_read_reg(hwif, addr);
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val = HINIC_PPF_ELECTION_CLEAR(val, IDX);
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ppf_election = HINIC_PPF_ELECTION_SET(attr->func_global_idx, IDX);
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val |= ppf_election;
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hinic_hwif_write_reg(hwif, addr, val);
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/* Check PPF */
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val = hinic_hwif_read_reg(hwif, addr);
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attr->ppf_idx = HINIC_PPF_ELECTION_GET(val, IDX);
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if (attr->ppf_idx == attr->func_global_idx)
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attr->func_type = TYPE_PPF;
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}
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static void init_db_area_idx(struct hinic_hwif *hwif)
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{
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struct hinic_free_db_area *free_db_area = &hwif->free_db_area;
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u32 db_max_areas = hwif->db_max_areas;
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u32 i;
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for (i = 0; i < db_max_areas; i++)
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free_db_area->db_idx[i] = i;
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free_db_area->alloc_pos = 0;
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free_db_area->return_pos = 0;
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free_db_area->num_free = db_max_areas;
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spin_lock_init(&free_db_area->idx_lock);
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}
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static int get_db_idx(struct hinic_hwif *hwif, u32 *idx)
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{
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struct hinic_free_db_area *free_db_area = &hwif->free_db_area;
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u32 pos;
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u32 pg_idx;
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spin_lock(&free_db_area->idx_lock);
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if (free_db_area->num_free == 0) {
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spin_unlock(&free_db_area->idx_lock);
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return -ENOMEM;
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}
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free_db_area->num_free--;
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pos = free_db_area->alloc_pos++;
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pos &= (hwif->db_max_areas - 1);
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pg_idx = free_db_area->db_idx[pos];
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free_db_area->db_idx[pos] = 0xFFFFFFFF;
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spin_unlock(&free_db_area->idx_lock);
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*idx = pg_idx;
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return 0;
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}
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static void free_db_idx(struct hinic_hwif *hwif, u32 idx)
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{
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struct hinic_free_db_area *free_db_area = &hwif->free_db_area;
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u32 pos;
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spin_lock(&free_db_area->idx_lock);
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pos = free_db_area->return_pos++;
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pos &= (hwif->db_max_areas - 1);
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free_db_area->db_idx[pos] = idx;
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free_db_area->num_free++;
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spin_unlock(&free_db_area->idx_lock);
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}
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void hinic_free_db_addr(void *hwdev, void __iomem *db_base)
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{
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struct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif;
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u32 idx = DB_IDX(db_base, hwif->db_base);
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free_db_idx(hwif, idx);
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}
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int hinic_alloc_db_addr(void *hwdev, void __iomem **db_base)
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{
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struct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif;
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u32 idx;
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int err;
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err = get_db_idx(hwif, &idx);
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if (err)
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return -EFAULT;
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*db_base = hwif->db_base + idx * HINIC_DB_PAGE_SIZE;
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return 0;
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}
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void hinic_set_msix_state(void *hwdev, u16 msix_idx, enum hinic_msix_state flag)
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{
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struct hinic_hwdev *hw = hwdev;
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struct hinic_hwif *hwif = hw->hwif;
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u32 offset = msix_idx * HINIC_PCI_MSIX_ENTRY_SIZE
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+ HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL;
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u32 mask_bits;
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/* vfio-pci does not mmap msi-x vector table to user space,
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* we can not access the space when kernel driver is vfio-pci
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*/
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if (hw->pcidev_hdl->kdrv == RTE_KDRV_VFIO)
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return;
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mask_bits = readl(hwif->intr_regs_base + offset);
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mask_bits &= ~HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT;
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if (flag)
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mask_bits |= HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT;
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writel(mask_bits, hwif->intr_regs_base + offset);
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}
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static void disable_all_msix(struct hinic_hwdev *hwdev)
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{
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u16 num_irqs = hwdev->hwif->attr.num_irqs;
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u16 i;
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for (i = 0; i < num_irqs; i++)
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hinic_set_msix_state(hwdev, i, HINIC_MSIX_DISABLE);
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}
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/**
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* Wait for up enable or disable doorbell flush finished.
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* @hwif: the hardware interface of a pci function device.
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* @states: Disable or Enable.
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*/
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int wait_until_doorbell_flush_states(struct hinic_hwif *hwif,
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enum hinic_doorbell_ctrl states)
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{
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unsigned long end;
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enum hinic_doorbell_ctrl db_ctrl;
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end = jiffies +
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msecs_to_jiffies(HINIC_WAIT_DOORBELL_AND_OUTBOUND_TIMEOUT);
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do {
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db_ctrl = hinic_get_doorbell_ctrl_status(hwif);
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if (db_ctrl == states)
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return 0;
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rte_delay_ms(1);
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} while (time_before(jiffies, end));
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return -ETIMEDOUT;
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}
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static int wait_until_doorbell_and_outbound_enabled(struct hinic_hwif *hwif)
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{
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unsigned long end;
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enum hinic_doorbell_ctrl db_ctrl;
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enum hinic_outbound_ctrl outbound_ctrl;
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end = jiffies +
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msecs_to_jiffies(HINIC_WAIT_DOORBELL_AND_OUTBOUND_TIMEOUT);
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do {
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db_ctrl = hinic_get_doorbell_ctrl_status(hwif);
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outbound_ctrl = hinic_get_outbound_ctrl_status(hwif);
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if (outbound_ctrl == ENABLE_OUTBOUND &&
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db_ctrl == ENABLE_DOORBELL)
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return 0;
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rte_delay_ms(1);
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} while (time_before(jiffies, end));
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return -ETIMEDOUT;
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}
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u16 hinic_global_func_id(void *hwdev)
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{
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struct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif;
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return hwif->attr.func_global_idx;
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}
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enum func_type hinic_func_type(void *hwdev)
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{
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struct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif;
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return hwif->attr.func_type;
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}
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u8 hinic_ppf_idx(void *hwdev)
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{
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struct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif;
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return hwif->attr.ppf_idx;
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}
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/**
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* hinic_dma_attr_entry_num - get number id of DMA attribute table.
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* @hwdev: the pointer to the private hardware device object.
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* Return: The number id of DMA attribute table.
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*/
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u8 hinic_dma_attr_entry_num(void *hwdev)
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{
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struct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif;
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return hwif->attr.num_dma_attr;
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}
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/**
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* hinic_init_hwif - initialize the hw interface
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* @hwdev: the pointer to the private hardware device object
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* @cfg_reg_base: base physical address of configuration registers
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* @intr_reg_base: base physical address of msi-x vector table
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* @db_base_phy: base physical address of doorbell registers
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* @db_base: base virtual address of doorbell registers
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* @dwqe_mapping: direct wqe io mapping address
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* Return: 0 - success, negative - failure
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*/
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static int hinic_init_hwif(struct hinic_hwdev *hwdev, void *cfg_reg_base,
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void *intr_reg_base, u64 db_base_phy,
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void *db_base, __rte_unused void *dwqe_mapping)
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{
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struct hinic_hwif *hwif;
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struct rte_pci_device *pci_dev;
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u64 db_bar_len;
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int err;
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pci_dev = (struct rte_pci_device *)(hwdev->pcidev_hdl);
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db_bar_len = pci_dev->mem_resource[HINIC_DB_MEM_BAR].len;
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hwif = hwdev->hwif;
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hwif->cfg_regs_base = (u8 __iomem *)cfg_reg_base;
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hwif->intr_regs_base = (u8 __iomem *)intr_reg_base;
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hwif->db_base_phy = db_base_phy;
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hwif->db_base = (u8 __iomem *)db_base;
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hwif->db_max_areas = db_bar_len / HINIC_DB_PAGE_SIZE;
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if (hwif->db_max_areas > HINIC_DB_MAX_AREAS)
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hwif->db_max_areas = HINIC_DB_MAX_AREAS;
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init_db_area_idx(hwif);
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get_hwif_attr(hwif);
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err = hwif_ready(hwdev);
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if (err) {
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PMD_DRV_LOG(ERR, "Hwif is not ready");
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goto hwif_ready_err;
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}
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err = wait_until_doorbell_and_outbound_enabled(hwif);
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if (err) {
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PMD_DRV_LOG(ERR, "Hw doorbell/outbound is disabled");
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goto hwif_ready_err;
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}
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if (!HINIC_IS_VF(hwdev))
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set_ppf(hwif);
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/* disable mgmt cpu report any event */
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hinic_set_pf_status(hwdev->hwif, HINIC_PF_STATUS_INIT);
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return 0;
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hwif_ready_err:
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spin_lock_deinit(&hwif->free_db_area.idx_lock);
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return err;
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}
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#define HINIC_HWIF_ATTR_REG_PRINT_NUM (6)
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#define HINIC_HWIF_APICMD_REG_PRINT_NUM (2)
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#define HINIC_HWIF_EQ_REG_PRINT_NUM (2)
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static void hinic_parse_hwif_attr(struct hinic_hwdev *hwdev)
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{
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struct hinic_hwif *hwif = hwdev->hwif;
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PMD_DRV_LOG(INFO, "Device %s hwif attribute:", hwdev->pcidev_hdl->name);
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PMD_DRV_LOG(INFO, "func_idx: %u, p2p_idx: %u, pciintf_idx: %u, "
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"vf_in_pf: %u, ppf_idx: %u, global_vf_id: %u, func_type: %u",
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hwif->attr.func_global_idx,
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hwif->attr.port_to_port_idx, hwif->attr.pci_intf_idx,
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hwif->attr.vf_in_pf, hwif->attr.ppf_idx,
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hwif->attr.global_vf_id_of_pf, hwif->attr.func_type);
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PMD_DRV_LOG(INFO, "num_aeqs:%u, num_ceqs:%u, num_irqs:%u, dma_attr:%u",
|
|
hwif->attr.num_aeqs, hwif->attr.num_ceqs,
|
|
hwif->attr.num_irqs, hwif->attr.num_dma_attr);
|
|
}
|
|
|
|
static void hinic_get_mmio(struct hinic_hwdev *hwdev, void **cfg_regs_base,
|
|
void **intr_base, void **db_base)
|
|
{
|
|
struct rte_pci_device *pci_dev = hwdev->pcidev_hdl;
|
|
uint64_t bar0_size;
|
|
uint64_t bar2_size;
|
|
uint64_t bar0_phy_addr;
|
|
uint64_t pagesize = sysconf(_SC_PAGESIZE);
|
|
|
|
*cfg_regs_base = pci_dev->mem_resource[HINIC_CFG_REGS_BAR].addr;
|
|
*intr_base = pci_dev->mem_resource[HINIC_INTR_MSI_BAR].addr;
|
|
*db_base = pci_dev->mem_resource[HINIC_DB_MEM_BAR].addr;
|
|
|
|
bar0_size = pci_dev->mem_resource[HINIC_CFG_REGS_BAR].len;
|
|
bar2_size = pci_dev->mem_resource[HINIC_INTR_MSI_BAR].len;
|
|
|
|
if (pagesize == PAGE_SIZE_64K && (bar0_size % pagesize != 0)) {
|
|
bar0_phy_addr =
|
|
pci_dev->mem_resource[HINIC_CFG_REGS_BAR].phys_addr;
|
|
if (bar0_phy_addr % pagesize != 0 &&
|
|
(bar0_size + bar2_size <= pagesize) &&
|
|
bar2_size >= bar0_size) {
|
|
*cfg_regs_base = (void *)((uint8_t *)(*intr_base)
|
|
+ bar2_size);
|
|
}
|
|
}
|
|
}
|
|
|
|
void hinic_hwif_res_free(struct hinic_hwdev *hwdev)
|
|
{
|
|
rte_free(hwdev->hwif);
|
|
hwdev->hwif = NULL;
|
|
}
|
|
|
|
int hinic_hwif_res_init(struct hinic_hwdev *hwdev)
|
|
{
|
|
int err = HINIC_ERROR;
|
|
void *cfg_regs_base, *db_base, *intr_base = NULL;
|
|
|
|
/* hinic related init */
|
|
hwdev->hwif = rte_zmalloc("hinic_hwif", sizeof(*hwdev->hwif),
|
|
RTE_CACHE_LINE_SIZE);
|
|
if (!hwdev->hwif) {
|
|
PMD_DRV_LOG(ERR, "Allocate hwif failed, dev_name: %s",
|
|
hwdev->pcidev_hdl->name);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
hinic_get_mmio(hwdev, &cfg_regs_base, &intr_base, &db_base);
|
|
|
|
err = hinic_init_hwif(hwdev, cfg_regs_base,
|
|
intr_base, 0, db_base, NULL);
|
|
if (err) {
|
|
PMD_DRV_LOG(ERR, "Initialize hwif failed, dev_name: %s",
|
|
hwdev->pcidev_hdl->name);
|
|
goto init_hwif_err;
|
|
}
|
|
|
|
/* disable msix interrupt in hw device */
|
|
disable_all_msix(hwdev);
|
|
|
|
/* print hwif attributes */
|
|
hinic_parse_hwif_attr(hwdev);
|
|
|
|
return HINIC_OK;
|
|
|
|
init_hwif_err:
|
|
rte_free(hwdev->hwif);
|
|
hwdev->hwif = NULL;
|
|
|
|
return err;
|
|
}
|
|
|
|
/**
|
|
* hinic_misx_intr_clear_resend_bit - clear interrupt resend configuration
|
|
* @hwdev: the hardware interface of a nic device
|
|
* @msix_idx: Index of msix interrupt
|
|
* @clear_resend_en: enable flag of clear resend configuration
|
|
*/
|
|
void hinic_misx_intr_clear_resend_bit(void *hwdev, u16 msix_idx,
|
|
u8 clear_resend_en)
|
|
{
|
|
struct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif;
|
|
u32 msix_ctrl = 0, addr;
|
|
|
|
msix_ctrl = HINIC_MSIX_CNT_SET(clear_resend_en, RESEND_TIMER);
|
|
|
|
addr = HINIC_CSR_MSIX_CNT_ADDR(msix_idx);
|
|
|
|
hinic_hwif_write_reg(hwif, addr, msix_ctrl);
|
|
}
|