7c6cca6b60
Add necessary changes to support new AVX512 specific ACL classify algorithm: - changes in meson.build to check that build tools (compiler, assembler, etc.) do properly support AVX512. - run-time checks to make sure target platform does support AVX512. - dummy rte_acl_classify_avx512() for targets where AVX512 implementation couldn't be properly supported. Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Bruce Richardson <bruce.richardson@intel.com>
60 lines
1.4 KiB
Meson
60 lines
1.4 KiB
Meson
# SPDX-License-Identifier: BSD-3-Clause
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# Copyright(c) 2017-2020 Intel Corporation
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# get binutils version for the workaround of Bug 97
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if not is_windows
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binutils_ok = run_command(binutils_avx512_check)
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if binutils_ok.returncode() != 0 and cc.has_argument('-mno-avx512f')
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machine_args += '-mno-avx512f'
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warning('Binutils error with AVX512 assembly, disabling AVX512 support')
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endif
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endif
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# we require SSE4.2 for DPDK
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if cc.get_define('__SSE4_2__', args: machine_args) == ''
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message('SSE 4.2 not enabled by default, explicitly enabling')
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machine_args += '-msse4'
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endif
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base_flags = ['SSE', 'SSE2', 'SSE3','SSSE3', 'SSE4_1', 'SSE4_2']
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foreach f:base_flags
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compile_time_cpuflags += ['RTE_CPUFLAG_' + f]
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endforeach
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optional_flags = [
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'AES',
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'AVX',
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'AVX2',
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'AVX512BW',
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'AVX512CD',
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'AVX512DQ',
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'AVX512F',
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'AVX512VL',
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'PCLMUL',
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'RDRND',
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'RDSEED',
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'VPCLMULQDQ',
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]
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foreach f:optional_flags
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if cc.get_define('__@0@__'.format(f), args: machine_args) == '1'
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if f == 'PCLMUL' # special case flags with different defines
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f = 'PCLMULQDQ'
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elif f == 'RDRND'
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f = 'RDRAND'
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endif
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compile_time_cpuflags += ['RTE_CPUFLAG_' + f]
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endif
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endforeach
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dpdk_conf.set('RTE_ARCH_X86', 1)
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if dpdk_conf.get('RTE_ARCH_64')
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dpdk_conf.set('RTE_ARCH_X86_64', 1)
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dpdk_conf.set('RTE_ARCH', 'x86_64')
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else
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dpdk_conf.set('RTE_ARCH_I686', 1)
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dpdk_conf.set('RTE_ARCH', 'i686')
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endif
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dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
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