4a22e6ee3d
This change adds automatic figure references to the docs. The figure numbers in the generated Html and PDF docs are now automatically numbered based on section. Requires Sphinx >= 1.3.1. The patch makes the following changes. * Changes image:: tag to figure:: and moves image caption to the figure. * Adds captions to figures that didn't previously have any. * Un-templates the |image-name| substitution definitions into explicit figure:: tags. They weren't used more than once anyway and Sphinx doesn't support them for figure. * Adds a target to each image that didn't previously have one so that they can be cross-referenced. * Renamed existing image target to match the image name for consistency. * Replaces the Figures lists with automatic :numref: :ref: entries to generate automatic numbering and captions. * Replaces "Figure" references with automatic :numref: references. Signed-off-by: John McNamara <john.mcnamara@intel.com>
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141 lines
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.. BSD LICENSE
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Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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.. _Mempool_Library:
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Mempool Library
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===============
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A memory pool is an allocator of a fixed-sized object.
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In the DPDK, it is identified by name and uses a ring to store free objects.
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It provides some other optional services such as a per-core object cache and
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an alignment helper to ensure that objects are padded to spread them equally on all DRAM or DDR3 channels.
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This library is used by the
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:ref:`Mbuf Library <Mbuf_Library>` and the
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:ref:`Environment Abstraction Layer <Environment_Abstraction_Layer>` (for logging history).
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Cookies
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-------
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In debug mode (CONFIG_RTE_LIBRTE_MEMPOOL_DEBUG is enabled), cookies are added at the beginning and end of allocated blocks.
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The allocated objects then contain overwrite protection fields to help debugging buffer overflows.
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Stats
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-----
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In debug mode (CONFIG_RTE_LIBRTE_MEMPOOL_DEBUG is enabled),
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statistics about get from/put in the pool are stored in the mempool structure.
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Statistics are per-lcore to avoid concurrent access to statistics counters.
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Memory Alignment Constraints
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----------------------------
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Depending on hardware memory configuration, performance can be greatly improved by adding a specific padding between objects.
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The objective is to ensure that the beginning of each object starts on a different channel and rank in memory so that all channels are equally loaded.
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This is particularly true for packet buffers when doing L3 forwarding or flow classification.
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Only the first 64 bytes are accessed, so performance can be increased by spreading the start addresses of objects among the different channels.
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The number of ranks on any DIMM is the number of independent sets of DRAMs that can be accessed for the full data bit-width of the DIMM.
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The ranks cannot be accessed simultaneously since they share the same data path.
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The physical layout of the DRAM chips on the DIMM itself does not necessarily relate to the number of ranks.
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When running an application, the EAL command line options provide the ability to add the number of memory channels and ranks.
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.. note::
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The command line must always have the number of memory channels specified for the processor.
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Examples of alignment for different DIMM architectures are shown in
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:numref:`figure_memory-management` and :numref:`figure_memory-management2`.
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.. _figure_memory-management:
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.. figure:: img/memory-management.*
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Two Channels and Quad-ranked DIMM Example
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In this case, the assumption is that a packet is 16 blocks of 64 bytes, which is not true.
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The Intel® 5520 chipset has three channels, so in most cases,
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no padding is required between objects (except for objects whose size are n x 3 x 64 bytes blocks).
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.. _figure_memory-management2:
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.. figure:: img/memory-management2.*
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Three Channels and Two Dual-ranked DIMM Example
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When creating a new pool, the user can specify to use this feature or not.
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Local Cache
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-----------
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In terms of CPU usage, the cost of multiple cores accessing a memory pool's ring of free buffers may be high
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since each access requires a compare-and-set (CAS) operation.
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To avoid having too many access requests to the memory pool's ring,
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the memory pool allocator can maintain a per-core cache and do bulk requests to the memory pool's ring,
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via the cache with many fewer locks on the actual memory pool structure.
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In this way, each core has full access to its own cache (with locks) of free objects and
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only when the cache fills does the core need to shuffle some of the free objects back to the pools ring or
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obtain more objects when the cache is empty.
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While this may mean a number of buffers may sit idle on some core's cache,
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the speed at which a core can access its own cache for a specific memory pool without locks provides performance gains.
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The cache is composed of a small, per-core table of pointers and its length (used as a stack).
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This cache can be enabled or disabled at creation of the pool.
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The maximum size of the cache is static and is defined at compilation time (CONFIG_RTE_MEMPOOL_CACHE_MAX_SIZE).
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:numref:`figure_mempool` shows a cache in operation.
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.. _figure_mempool:
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.. figure:: img/mempool.*
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A mempool in Memory with its Associated Ring
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Use Cases
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---------
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All allocations that require a high level of performance should use a pool-based memory allocator.
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Below are some examples:
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* :ref:`Mbuf Library <Mbuf_Library>`
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* :ref:`Environment Abstraction Layer <Environment_Abstraction_Layer>` , for logging service
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* Any application that needs to allocate fixed-sized objects in the data plane and that will be continuously utilized by the system.
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