31246a328f
Add device arguments to lock NPA aura and pool contexts in NDC cache. The device args take hexadecimal bitmask where each bit represent the corresponding aura/pool id. Example: -w 0002:02:00.0,npa_lock_mask=0xf // Lock first 4 aura/pool ctx Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com> Acked-by: Jerin Jacob <jerinj@marvell.com>
194 lines
4.6 KiB
C
194 lines
4.6 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#include <inttypes.h>
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#include <math.h>
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#include "otx2_ethdev.h"
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static int
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parse_flow_max_priority(const char *key, const char *value, void *extra_args)
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{
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RTE_SET_USED(key);
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uint16_t val;
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val = atoi(value);
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/* Limit the max priority to 32 */
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if (val < 1 || val > 32)
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return -EINVAL;
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*(uint16_t *)extra_args = val;
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return 0;
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}
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static int
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parse_flow_prealloc_size(const char *key, const char *value, void *extra_args)
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{
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RTE_SET_USED(key);
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uint16_t val;
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val = atoi(value);
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/* Limit the prealloc size to 32 */
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if (val < 1 || val > 32)
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return -EINVAL;
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*(uint16_t *)extra_args = val;
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return 0;
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}
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static int
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parse_reta_size(const char *key, const char *value, void *extra_args)
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{
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RTE_SET_USED(key);
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uint32_t val;
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val = atoi(value);
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if (val <= ETH_RSS_RETA_SIZE_64)
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val = ETH_RSS_RETA_SIZE_64;
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else if (val > ETH_RSS_RETA_SIZE_64 && val <= ETH_RSS_RETA_SIZE_128)
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val = ETH_RSS_RETA_SIZE_128;
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else if (val > ETH_RSS_RETA_SIZE_128 && val <= ETH_RSS_RETA_SIZE_256)
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val = ETH_RSS_RETA_SIZE_256;
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else
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val = NIX_RSS_RETA_SIZE;
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*(uint16_t *)extra_args = val;
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return 0;
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}
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static int
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parse_ipsec_in_max_spi(const char *key, const char *value, void *extra_args)
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{
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RTE_SET_USED(key);
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uint32_t val;
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val = atoi(value);
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*(uint16_t *)extra_args = val;
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return 0;
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}
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static int
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parse_flag(const char *key, const char *value, void *extra_args)
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{
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RTE_SET_USED(key);
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*(uint16_t *)extra_args = atoi(value);
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return 0;
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}
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static int
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parse_sqb_count(const char *key, const char *value, void *extra_args)
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{
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RTE_SET_USED(key);
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uint32_t val;
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val = atoi(value);
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if (val < NIX_MIN_SQB || val > NIX_MAX_SQB)
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return -EINVAL;
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*(uint16_t *)extra_args = val;
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return 0;
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}
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static int
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parse_switch_header_type(const char *key, const char *value, void *extra_args)
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{
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RTE_SET_USED(key);
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if (strcmp(value, "higig2") == 0)
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*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_HIGIG;
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if (strcmp(value, "dsa") == 0)
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*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_EDSA;
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if (strcmp(value, "chlen90b") == 0)
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*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_LEN_90B;
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return 0;
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}
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#define OTX2_RSS_RETA_SIZE "reta_size"
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#define OTX2_IPSEC_IN_MAX_SPI "ipsec_in_max_spi"
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#define OTX2_SCL_ENABLE "scalar_enable"
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#define OTX2_MAX_SQB_COUNT "max_sqb_count"
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#define OTX2_FLOW_PREALLOC_SIZE "flow_prealloc_size"
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#define OTX2_FLOW_MAX_PRIORITY "flow_max_priority"
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#define OTX2_SWITCH_HEADER_TYPE "switch_header"
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#define OTX2_RSS_TAG_AS_XOR "tag_as_xor"
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int
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otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)
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{
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uint16_t rss_size = NIX_RSS_RETA_SIZE;
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uint16_t sqb_count = NIX_MAX_SQB;
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uint16_t flow_prealloc_size = 8;
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uint16_t switch_header_type = 0;
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uint16_t flow_max_priority = 3;
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uint16_t ipsec_in_max_spi = 1;
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uint16_t scalar_enable = 0;
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uint16_t rss_tag_as_xor = 0;
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struct rte_kvargs *kvlist;
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if (devargs == NULL)
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goto null_devargs;
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kvlist = rte_kvargs_parse(devargs->args, NULL);
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if (kvlist == NULL)
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goto exit;
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rte_kvargs_process(kvlist, OTX2_RSS_RETA_SIZE,
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&parse_reta_size, &rss_size);
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rte_kvargs_process(kvlist, OTX2_IPSEC_IN_MAX_SPI,
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&parse_ipsec_in_max_spi, &ipsec_in_max_spi);
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rte_kvargs_process(kvlist, OTX2_SCL_ENABLE,
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&parse_flag, &scalar_enable);
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rte_kvargs_process(kvlist, OTX2_MAX_SQB_COUNT,
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&parse_sqb_count, &sqb_count);
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rte_kvargs_process(kvlist, OTX2_FLOW_PREALLOC_SIZE,
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&parse_flow_prealloc_size, &flow_prealloc_size);
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rte_kvargs_process(kvlist, OTX2_FLOW_MAX_PRIORITY,
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&parse_flow_max_priority, &flow_max_priority);
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rte_kvargs_process(kvlist, OTX2_SWITCH_HEADER_TYPE,
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&parse_switch_header_type, &switch_header_type);
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rte_kvargs_process(kvlist, OTX2_RSS_TAG_AS_XOR,
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&parse_flag, &rss_tag_as_xor);
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otx2_parse_common_devargs(kvlist);
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rte_kvargs_free(kvlist);
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null_devargs:
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dev->ipsec_in_max_spi = ipsec_in_max_spi;
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dev->scalar_ena = scalar_enable;
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dev->rss_tag_as_xor = rss_tag_as_xor;
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dev->max_sqb_count = sqb_count;
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dev->rss_info.rss_size = rss_size;
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dev->npc_flow.flow_prealloc_size = flow_prealloc_size;
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dev->npc_flow.flow_max_priority = flow_max_priority;
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dev->npc_flow.switch_header_type = switch_header_type;
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return 0;
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exit:
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return -EINVAL;
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}
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RTE_PMD_REGISTER_PARAM_STRING(net_octeontx2,
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OTX2_RSS_RETA_SIZE "=<64|128|256>"
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OTX2_IPSEC_IN_MAX_SPI "=<1-65535>"
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OTX2_SCL_ENABLE "=1"
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OTX2_MAX_SQB_COUNT "=<8-512>"
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OTX2_FLOW_PREALLOC_SIZE "=<1-32>"
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OTX2_FLOW_MAX_PRIORITY "=<1-32>"
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OTX2_SWITCH_HEADER_TYPE "=<higig2|dsa|chlen90b>"
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OTX2_RSS_TAG_AS_XOR "=1"
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OTX2_NPA_LOCK_MASK "=<1-65535>");
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