e2b4925ef7
This commit checks the for DR E-Switch support. The support is based on both Device and Kernel. This commit also enables the user to manually disable this this feature. Signed-off-by: Ori Kam <orika@mellanox.com> Acked-by: Yongseok Koh <yskoh@mellanox.com>
570 lines
21 KiB
C
570 lines
21 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2015 6WIND S.A.
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* Copyright 2015 Mellanox Technologies, Ltd
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*/
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#ifndef RTE_PMD_MLX5_H_
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#define RTE_PMD_MLX5_H_
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#include <stddef.h>
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#include <stdint.h>
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#include <limits.h>
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#include <net/if.h>
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#include <netinet/in.h>
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#include <sys/queue.h>
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/* Verbs header. */
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/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
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#ifdef PEDANTIC
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#pragma GCC diagnostic ignored "-Wpedantic"
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#endif
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#include <infiniband/verbs.h>
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#ifdef PEDANTIC
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#pragma GCC diagnostic error "-Wpedantic"
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#endif
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#include <rte_pci.h>
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#include <rte_ether.h>
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#include <rte_ethdev_driver.h>
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#include <rte_rwlock.h>
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#include <rte_interrupts.h>
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#include <rte_errno.h>
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#include <rte_flow.h>
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#include "mlx5_utils.h"
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#include "mlx5_mr.h"
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#include "mlx5_autoconf.h"
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#include "mlx5_defs.h"
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enum {
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PCI_VENDOR_ID_MELLANOX = 0x15b3,
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};
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enum {
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PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
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PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
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PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
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PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
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PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
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PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
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PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
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PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
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PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
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PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
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PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
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PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
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};
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/* Request types for IPC. */
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enum mlx5_mp_req_type {
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MLX5_MP_REQ_VERBS_CMD_FD = 1,
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MLX5_MP_REQ_CREATE_MR,
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MLX5_MP_REQ_START_RXTX,
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MLX5_MP_REQ_STOP_RXTX,
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};
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/* Pameters for IPC. */
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struct mlx5_mp_param {
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enum mlx5_mp_req_type type;
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int port_id;
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int result;
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RTE_STD_C11
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union {
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uintptr_t addr; /* MLX5_MP_REQ_CREATE_MR */
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} args;
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};
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/** Request timeout for IPC. */
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#define MLX5_MP_REQ_TIMEOUT_SEC 5
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/** Key string for IPC. */
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#define MLX5_MP_NAME "net_mlx5_mp"
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/* Recognized Infiniband device physical port name types. */
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enum mlx5_phys_port_name_type {
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MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
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MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
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MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
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MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
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MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
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};
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/** Switch information returned by mlx5_nl_switch_info(). */
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struct mlx5_switch_info {
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uint32_t master:1; /**< Master device. */
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uint32_t representor:1; /**< Representor device. */
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enum mlx5_phys_port_name_type name_type; /** < Port name type. */
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int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
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int32_t port_name; /**< Representor port name. */
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uint64_t switch_id; /**< Switch identifier. */
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};
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LIST_HEAD(mlx5_dev_list, mlx5_priv);
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/* Shared data between primary and secondary processes. */
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struct mlx5_shared_data {
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rte_spinlock_t lock;
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/* Global spinlock for primary and secondary processes. */
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int init_done; /* Whether primary has done initialization. */
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unsigned int secondary_cnt; /* Number of secondary processes init'd. */
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struct mlx5_dev_list mem_event_cb_list;
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rte_rwlock_t mem_event_rwlock;
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};
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/* Per-process data structure, not visible to other processes. */
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struct mlx5_local_data {
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int init_done; /* Whether a secondary has done initialization. */
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};
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extern struct mlx5_shared_data *mlx5_shared_data;
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struct mlx5_counter_ctrl {
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/* Name of the counter. */
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char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
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/* Name of the counter on the device table. */
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char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
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uint32_t ib:1; /**< Nonzero for IB counters. */
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};
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struct mlx5_xstats_ctrl {
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/* Number of device stats. */
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uint16_t stats_n;
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/* Number of device stats identified by PMD. */
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uint16_t mlx5_stats_n;
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/* Index in the device counters table. */
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uint16_t dev_table_idx[MLX5_MAX_XSTATS];
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uint64_t base[MLX5_MAX_XSTATS];
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struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
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};
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struct mlx5_stats_ctrl {
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/* Base for imissed counter. */
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uint64_t imissed_base;
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};
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/* devx counter object */
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struct mlx5_devx_counter_set {
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struct mlx5dv_devx_obj *obj;
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int id; /* Flow counter ID */
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};
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/* HCA attributes. */
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struct mlx5_hca_attr {
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uint32_t eswitch_manager:1;
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};
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/* Flow list . */
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TAILQ_HEAD(mlx5_flows, rte_flow);
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/* Default PMD specific parameter value. */
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#define MLX5_ARG_UNSET (-1)
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/*
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* Device configuration structure.
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*
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* Merged configuration from:
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*
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* - Device capabilities,
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* - User device parameters disabled features.
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*/
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struct mlx5_dev_config {
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unsigned int hw_csum:1; /* Checksum offload is supported. */
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unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
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unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
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unsigned int hw_padding:1; /* End alignment padding is supported. */
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unsigned int vf:1; /* This is a VF. */
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unsigned int tunnel_en:1;
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/* Whether tunnel stateless offloads are supported. */
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unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
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unsigned int cqe_comp:1; /* CQE compression is enabled. */
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unsigned int cqe_pad:1; /* CQE padding is enabled. */
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unsigned int tso:1; /* Whether TSO is supported. */
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unsigned int tx_vec_en:1; /* Tx vector is enabled. */
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unsigned int rx_vec_en:1; /* Rx vector is enabled. */
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unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
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unsigned int mr_ext_memseg_en:1;
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/* Whether memseg should be extended for MR creation. */
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unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
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unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
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unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
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unsigned int dv_flow_en:1; /* Enable DV flow. */
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unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
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unsigned int devx:1; /* Whether devx interface is available or not. */
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struct {
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unsigned int enabled:1; /* Whether MPRQ is enabled. */
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unsigned int stride_num_n; /* Number of strides. */
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unsigned int min_stride_size_n; /* Min size of a stride. */
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unsigned int max_stride_size_n; /* Max size of a stride. */
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unsigned int max_memcpy_len;
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/* Maximum packet size to memcpy Rx packets. */
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unsigned int min_rxqs_num;
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/* Rx queue count threshold to enable MPRQ. */
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} mprq; /* Configurations for Multi-Packet RQ. */
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int mps; /* Multi-packet send supported mode. */
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unsigned int flow_prio; /* Number of flow priorities. */
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unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
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unsigned int ind_table_max_size; /* Maximum indirection table size. */
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int txq_inline; /* Maximum packet size for inlining. */
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int txqs_inline; /* Queue number threshold for inlining. */
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int txqs_vec; /* Queue number threshold for vectorized Tx. */
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int inline_max_packet_sz; /* Max packet size for inlining. */
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struct mlx5_hca_attr hca_attr; /* HCA attributes. */
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};
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/**
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* Type of objet being allocated.
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*/
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enum mlx5_verbs_alloc_type {
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MLX5_VERBS_ALLOC_TYPE_NONE,
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MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
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MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
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};
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/**
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* Verbs allocator needs a context to know in the callback which kind of
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* resources it is allocating.
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*/
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struct mlx5_verbs_alloc_ctx {
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enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
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const void *obj; /* Pointer to the DPDK object. */
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};
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LIST_HEAD(mlx5_mr_list, mlx5_mr);
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/* Flow drop context necessary due to Verbs API. */
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struct mlx5_drop {
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struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
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struct mlx5_rxq_ibv *rxq; /* Verbs Rx queue. */
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};
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struct mlx5_flow_tcf_context;
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/* Per port data of shared IB device. */
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struct mlx5_ibv_shared_port {
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uint32_t ih_port_id;
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/*
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* Interrupt handler port_id. Used by shared interrupt
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* handler to find the corresponding rte_eth device
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* by IB port index. If value is equal or greater
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* RTE_MAX_ETHPORTS it means there is no subhandler
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* installed for specified IB port index.
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*/
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};
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/* Table structure. */
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struct mlx5_flow_tbl_resource {
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void *obj; /**< Pointer to DR table object. */
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rte_atomic32_t refcnt; /**< Reference counter. */
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};
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#define MLX5_MAX_TABLES 1024
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#define MLX5_MAX_TABLES_FDB 32
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#define MLX5_GROUP_FACTOR 1
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/*
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* Shared Infiniband device context for Master/Representors
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* which belong to same IB device with multiple IB ports.
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**/
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struct mlx5_ibv_shared {
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LIST_ENTRY(mlx5_ibv_shared) next;
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uint32_t refcnt;
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uint32_t devx:1; /* Opened with DV. */
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uint32_t max_port; /* Maximal IB device port index. */
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struct ibv_context *ctx; /* Verbs/DV context. */
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struct ibv_pd *pd; /* Protection Domain. */
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char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
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char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
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struct ibv_device_attr_ex device_attr; /* Device properties. */
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/* Shared DV/DR flow data section. */
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pthread_mutex_t dv_mutex; /* DV context mutex. */
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uint32_t dv_refcnt; /* DV/DR data reference counter. */
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void *fdb_ns; /* FDB Direct Rules name space handle. */
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struct mlx5_flow_tbl_resource fdb_tbl[MLX5_MAX_TABLES_FDB];
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/* FDB Direct Rules tables. */
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void *rx_ns; /* RX Direct Rules name space handle. */
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struct mlx5_flow_tbl_resource rx_tbl[MLX5_MAX_TABLES];
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/* RX Direct Rules tables. */
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void *tx_ns; /* TX Direct Rules name space handle. */
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struct mlx5_flow_tbl_resource tx_tbl[MLX5_MAX_TABLES];
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/* TX Direct Rules tables/ */
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LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
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LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
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LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
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LIST_HEAD(tag, mlx5_flow_dv_tag_resource) tags;
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LIST_HEAD(jump, mlx5_flow_dv_jump_tbl_resource) jump_tbl;
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/* Shared interrupt handler section. */
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pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
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uint32_t intr_cnt; /* Interrupt handler reference counter. */
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struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
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struct mlx5_ibv_shared_port port[]; /* per device port data array. */
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};
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/* Per-process private structure. */
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struct mlx5_proc_priv {
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size_t uar_table_sz;
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/* Size of UAR register table. */
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void *uar_table[];
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/* Table of UAR registers for each process. */
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};
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#define MLX5_PROC_PRIV(port_id) \
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((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
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struct mlx5_priv {
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LIST_ENTRY(mlx5_priv) mem_event_cb;
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/**< Called by memory event callback. */
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struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
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struct mlx5_ibv_shared *sh; /* Shared IB device context. */
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uint32_t ibv_port; /* IB device port number. */
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struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
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BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
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/* Bit-field of MAC addresses owned by the PMD. */
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uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
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unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
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/* Device properties. */
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uint16_t mtu; /* Configured MTU. */
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unsigned int isolated:1; /* Whether isolated mode is enabled. */
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unsigned int representor:1; /* Device is a port representor. */
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unsigned int master:1; /* Device is a E-Switch master. */
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unsigned int dr_shared:1; /* DV/DR data is shared. */
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uint16_t domain_id; /* Switch domain identifier. */
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uint16_t vport_id; /* Associated VF vport index (if any). */
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int32_t representor_id; /* Port representor identifier. */
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/* RX/TX queues. */
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unsigned int rxqs_n; /* RX queues array size. */
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unsigned int txqs_n; /* TX queues array size. */
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struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
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struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
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struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
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struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
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unsigned int (*reta_idx)[]; /* RETA index table. */
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unsigned int reta_idx_n; /* RETA index size. */
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struct mlx5_drop drop_queue; /* Flow drop queues. */
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struct mlx5_flows flows; /* RTE Flow rules. */
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struct mlx5_flows ctrl_flows; /* Control flow rules. */
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LIST_HEAD(counters, mlx5_flow_counter) flow_counters;
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/* Flow counters. */
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struct {
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uint32_t dev_gen; /* Generation number to flush local caches. */
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rte_rwlock_t rwlock; /* MR Lock. */
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struct mlx5_mr_btree cache; /* Global MR cache table. */
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struct mlx5_mr_list mr_list; /* Registered MR list. */
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struct mlx5_mr_list mr_free_list; /* Freed MR list. */
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} mr;
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LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
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LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
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LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
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LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
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LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
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/* Verbs Indirection tables. */
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LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
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/* Pointer to next element. */
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rte_atomic32_t refcnt; /**< Reference counter. */
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struct ibv_flow_action *verbs_action;
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/**< Verbs modify header action object. */
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uint8_t ft_type; /**< Flow table type, Rx or Tx. */
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/* Tags resources cache. */
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uint32_t link_speed_capa; /* Link speed capabilities. */
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struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
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struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
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struct mlx5_dev_config config; /* Device configuration. */
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struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
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/* Context for Verbs allocator. */
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int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
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int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
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uint32_t nl_sn; /* Netlink message sequence number. */
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#ifndef RTE_ARCH_64
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rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
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rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
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/* UAR same-page access control required in 32bit implementations. */
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#endif
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struct mlx5_flow_tcf_context *tcf_context; /* TC flower context. */
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};
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#define PORT_ID(priv) ((priv)->dev_data->port_id)
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#define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
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/* mlx5.c */
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int mlx5_getenv_int(const char *);
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int mlx5_proc_priv_init(struct rte_eth_dev *dev);
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/* mlx5_ethdev.c */
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int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
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int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
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unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
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int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
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int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
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int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
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unsigned int flags);
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int mlx5_dev_configure(struct rte_eth_dev *dev);
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void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
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int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
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const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
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int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
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int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
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int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
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int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
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struct rte_eth_fc_conf *fc_conf);
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int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
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struct rte_eth_fc_conf *fc_conf);
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int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device,
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struct rte_pci_addr *pci_addr);
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void mlx5_dev_link_status_handler(void *arg);
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void mlx5_dev_interrupt_handler(void *arg);
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void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
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void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
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int mlx5_set_link_down(struct rte_eth_dev *dev);
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int mlx5_set_link_up(struct rte_eth_dev *dev);
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int mlx5_is_removed(struct rte_eth_dev *dev);
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eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
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eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
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unsigned int mlx5_dev_to_port_id(const struct rte_device *dev,
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uint16_t *port_list,
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unsigned int port_list_n);
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int mlx5_sysfs_switch_info(unsigned int ifindex,
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struct mlx5_switch_info *info);
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void mlx5_sysfs_check_switch_info(bool device_dir,
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struct mlx5_switch_info *switch_info);
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void mlx5_nl_check_switch_info(bool nun_vf_set,
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struct mlx5_switch_info *switch_info);
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void mlx5_translate_port_name(const char *port_name_in,
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struct mlx5_switch_info *port_info_out);
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/* mlx5_mac.c */
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int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[ETHER_ADDR_LEN]);
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void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
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int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
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uint32_t index, uint32_t vmdq);
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int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr);
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int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
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struct ether_addr *mc_addr_set, uint32_t nb_mc_addr);
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/* mlx5_rss.c */
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int mlx5_rss_hash_update(struct rte_eth_dev *dev,
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struct rte_eth_rss_conf *rss_conf);
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int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
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struct rte_eth_rss_conf *rss_conf);
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int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
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int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
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struct rte_eth_rss_reta_entry64 *reta_conf,
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uint16_t reta_size);
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int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
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struct rte_eth_rss_reta_entry64 *reta_conf,
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uint16_t reta_size);
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/* mlx5_rxmode.c */
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void mlx5_promiscuous_enable(struct rte_eth_dev *dev);
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void mlx5_promiscuous_disable(struct rte_eth_dev *dev);
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void mlx5_allmulticast_enable(struct rte_eth_dev *dev);
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void mlx5_allmulticast_disable(struct rte_eth_dev *dev);
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/* mlx5_stats.c */
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void mlx5_stats_init(struct rte_eth_dev *dev);
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int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
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void mlx5_stats_reset(struct rte_eth_dev *dev);
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int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
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unsigned int n);
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void mlx5_xstats_reset(struct rte_eth_dev *dev);
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int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
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struct rte_eth_xstat_name *xstats_names,
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unsigned int n);
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/* mlx5_vlan.c */
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int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
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void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
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int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
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/* mlx5_trigger.c */
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int mlx5_dev_start(struct rte_eth_dev *dev);
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void mlx5_dev_stop(struct rte_eth_dev *dev);
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int mlx5_traffic_enable(struct rte_eth_dev *dev);
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void mlx5_traffic_disable(struct rte_eth_dev *dev);
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int mlx5_traffic_restart(struct rte_eth_dev *dev);
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/* mlx5_flow.c */
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int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
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void mlx5_flow_print(struct rte_flow *flow);
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int mlx5_flow_validate(struct rte_eth_dev *dev,
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const struct rte_flow_attr *attr,
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const struct rte_flow_item items[],
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const struct rte_flow_action actions[],
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struct rte_flow_error *error);
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struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
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const struct rte_flow_attr *attr,
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const struct rte_flow_item items[],
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const struct rte_flow_action actions[],
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struct rte_flow_error *error);
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int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
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struct rte_flow_error *error);
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void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
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int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
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int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
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const struct rte_flow_action *action, void *data,
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|
struct rte_flow_error *error);
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int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
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|
struct rte_flow_error *error);
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int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
|
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enum rte_filter_type filter_type,
|
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enum rte_filter_op filter_op,
|
|
void *arg);
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int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
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void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
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int mlx5_flow_verify(struct rte_eth_dev *dev);
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int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
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|
struct rte_flow_item_eth *eth_spec,
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|
struct rte_flow_item_eth *eth_mask,
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|
struct rte_flow_item_vlan *vlan_spec,
|
|
struct rte_flow_item_vlan *vlan_mask);
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int mlx5_ctrl_flow(struct rte_eth_dev *dev,
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|
struct rte_flow_item_eth *eth_spec,
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|
struct rte_flow_item_eth *eth_mask);
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int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
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|
void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
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/* mlx5_mp.c */
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void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
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void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
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int mlx5_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr);
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|
int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev);
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|
void mlx5_mp_init_primary(void);
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|
void mlx5_mp_uninit_primary(void);
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|
void mlx5_mp_init_secondary(void);
|
|
void mlx5_mp_uninit_secondary(void);
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|
|
|
/* mlx5_nl.c */
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|
|
|
int mlx5_nl_init(int protocol);
|
|
int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
|
|
uint32_t index);
|
|
int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct ether_addr *mac,
|
|
uint32_t index);
|
|
void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
|
|
void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
|
|
int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
|
|
int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
|
|
unsigned int mlx5_nl_portnum(int nl, const char *name);
|
|
unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex);
|
|
int mlx5_nl_switch_info(int nl, unsigned int ifindex,
|
|
struct mlx5_switch_info *info);
|
|
|
|
/* mlx5_devx_cmds.c */
|
|
|
|
int mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
|
|
struct mlx5_devx_counter_set *dcx);
|
|
int mlx5_devx_cmd_flow_counter_free(struct mlx5dv_devx_obj *obj);
|
|
int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_counter_set *dcx,
|
|
int clear,
|
|
uint64_t *pkts, uint64_t *bytes);
|
|
int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
|
|
struct mlx5_hca_attr *attr);
|
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#endif /* RTE_PMD_MLX5_H_ */
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