e41856b515
Current hardware protection is based on pthread mutex which work just for situation of multi-thread in one process. In multi-process environment, hardware state machine would be corrupted by concurrent access, that means original pthread mutex mechanism need be enhanced. The major modifications in this patch are list below: 1. Create a mutex for adapter in shared memory named "mutex.IFPGA:domain:bus:dev.func" when device is probed. 2. Create a shared memory named "IFPGA:domain:bus:dev.func" during opae adapter is initializing. There is a reference count in shared memory. Shared memory will be destroyed once reference count turned to zero. 3. Two mutexs are created in shared memory and initialized with flag PTHREAD_PROCESS_SHARED. One for SPI and the other for I2C. They will be passed to SPI and I2C driver subsequently. 4. DTB data in flash will be cached in shared memory. Then MAX10 driver can read DTB from shared memory instead of flash. This avoid confliction of concurrent flash access between hardware and software. Signed-off-by: Wei Huang <wei.huang@intel.com> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> Acked-by: Rosen Xu <rosen.xu@intel.com>
133 lines
4.3 KiB
C
133 lines
4.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2010-2019 Intel Corporation
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*/
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#ifndef _OPAE_I2C_H
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#define _OPAE_I2C_H
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#include "opae_osdep.h"
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#define ALTERA_I2C_TFR_CMD 0x00 /* Transfer Command register */
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#define ALTERA_I2C_TFR_CMD_STA BIT(9) /* send START before byte */
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#define ALTERA_I2C_TFR_CMD_STO BIT(8) /* send STOP after byte */
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#define ALTERA_I2C_TFR_CMD_RW_D BIT(0) /* Direction of transfer */
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#define ALTERA_I2C_RX_DATA 0x04 /* RX data FIFO register */
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#define ALTERA_I2C_CTRL 0x8 /* Control register */
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#define ALTERA_I2C_CTRL_RXT_SHFT 4 /* RX FIFO Threshold */
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#define ALTERA_I2C_CTRL_TCT_SHFT 2 /* TFER CMD FIFO Threshold */
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#define ALTERA_I2C_CTRL_BSPEED BIT(1) /* Bus Speed */
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#define ALTERA_I2C_CTRL_EN BIT(0) /* Enable Core */
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#define ALTERA_I2C_ISER 0xc /* Interrupt Status Enable register */
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#define ALTERA_I2C_ISER_RXOF_EN BIT(4) /* Enable RX OVERFLOW IRQ */
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#define ALTERA_I2C_ISER_ARB_EN BIT(3) /* Enable ARB LOST IRQ */
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#define ALTERA_I2C_ISER_NACK_EN BIT(2) /* Enable NACK DET IRQ */
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#define ALTERA_I2C_ISER_RXRDY_EN BIT(1) /* Enable RX Ready IRQ */
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#define ALTERA_I2C_ISER_TXRDY_EN BIT(0) /* Enable TX Ready IRQ */
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#define ALTERA_I2C_ISR 0x10 /* Interrupt Status register */
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#define ALTERA_I2C_ISR_RXOF BIT(4) /* RX OVERFLOW */
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#define ALTERA_I2C_ISR_ARB BIT(3) /* ARB LOST */
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#define ALTERA_I2C_ISR_NACK BIT(2) /* NACK DET */
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#define ALTERA_I2C_ISR_RXRDY BIT(1) /* RX Ready */
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#define ALTERA_I2C_ISR_TXRDY BIT(0) /* TX Ready */
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#define ALTERA_I2C_STATUS 0x14 /* Status register */
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#define ALTERA_I2C_STAT_CORE BIT(0) /* Core Status */
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#define ALTERA_I2C_TC_FIFO_LVL 0x18 /* Transfer FIFO LVL register */
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#define ALTERA_I2C_RX_FIFO_LVL 0x1c /* Receive FIFO LVL register */
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#define ALTERA_I2C_SCL_LOW 0x20 /* SCL low count register */
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#define ALTERA_I2C_SCL_HIGH 0x24 /* SCL high count register */
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#define ALTERA_I2C_SDA_HOLD 0x28 /* SDA hold count register */
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#define ALTERA_I2C_ALL_IRQ (ALTERA_I2C_ISR_RXOF | ALTERA_I2C_ISR_ARB | \
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ALTERA_I2C_ISR_NACK | ALTERA_I2C_ISR_RXRDY | \
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ALTERA_I2C_ISR_TXRDY)
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#define ALTERA_I2C_THRESHOLD 0
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#define ALTERA_I2C_DFLT_FIFO_SZ 8
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#define ALTERA_I2C_TIMEOUT_US 250000 /* 250ms */
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#define I2C_PARAM 0x8
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#define I2C_CTRL 0x10
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#define I2C_CTRL_R BIT_ULL(9)
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#define I2C_CTRL_W BIT_ULL(8)
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#define I2C_CTRL_ADDR_MASK GENMASK_ULL(3, 0)
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#define I2C_READ 0x18
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#define I2C_READ_DATA_VALID BIT_ULL(32)
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#define I2C_READ_DATA_MASK GENMASK_ULL(31, 0)
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#define I2C_WRITE 0x20
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#define I2C_WRITE_DATA_MASK GENMASK_ULL(31, 0)
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#define ALTERA_I2C_100KHZ 0
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#define ALTERA_I2C_400KHZ 1
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/* i2c slave using 16bit address */
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#define I2C_FLAG_ADDR16 1
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#define I2C_XFER_RETRY 10
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struct i2c_core_param {
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union {
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u64 info;
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struct {
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u16 fifo_depth:9;
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u8 interface:1;
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/*reference clock of I2C core in MHz*/
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u32 ref_clk:10;
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/*Max I2C interface freq*/
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u8 max_req:4;
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u64 devid:32;
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/* number of MAC address*/
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u8 nu_macs:8;
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};
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};
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};
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struct altera_i2c_dev {
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u8 *base;
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struct i2c_core_param i2c_param;
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u32 fifo_size;
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u32 bus_clk_rate; /* i2c bus clock */
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u32 i2c_clk; /* i2c input clock */
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struct i2c_msg *msg;
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size_t msg_len;
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int msg_err;
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u32 isr_mask;
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u8 *buf;
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int (*xfer)(struct altera_i2c_dev *dev, struct i2c_msg *msg, int num);
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pthread_mutex_t lock;
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pthread_mutex_t *mutex; /* multi-process mutex from adapter */
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};
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/**
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* struct i2c_msg: an I2C message
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*/
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struct i2c_msg {
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unsigned int addr;
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unsigned int flags;
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unsigned int len;
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u8 *buf;
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};
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#define I2C_MAX_OFFSET_LEN 4
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enum i2c_msg_flags {
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I2C_M_TEN = 0x0010, /*ten-bit chip address*/
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I2C_M_RD = 0x0001, /*read data*/
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I2C_M_STOP = 0x8000, /*send stop after this message*/
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};
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struct altera_i2c_dev *altera_i2c_probe(void *base);
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void altera_i2c_remove(struct altera_i2c_dev *dev);
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int i2c_read(struct altera_i2c_dev *dev, int flags, unsigned int slave_addr,
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u32 offset, u8 *buf, u32 count);
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int i2c_write(struct altera_i2c_dev *dev, int flags, unsigned int slave_addr,
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u32 offset, u8 *buffer, int len);
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int i2c_read8(struct altera_i2c_dev *dev, unsigned int slave_addr, u32 offset,
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u8 *buf, u32 count);
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int i2c_read16(struct altera_i2c_dev *dev, unsigned int slave_addr, u32 offset,
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u8 *buf, u32 count);
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int i2c_write8(struct altera_i2c_dev *dev, unsigned int slave_addr, u32 offset,
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u8 *buf, u32 count);
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int i2c_write16(struct altera_i2c_dev *dev, unsigned int slave_addr, u32 offset,
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u8 *buf, u32 count);
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#endif
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