e47565a78e
Add list of environment variables used by cnxk drivers. Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
638 lines
22 KiB
ReStructuredText
638 lines
22 KiB
ReStructuredText
.. SPDX-License-Identifier: BSD-3-Clause
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Copyright(C) 2021 Marvell.
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Marvell cnxk platform guide
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===========================
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This document gives an overview of **Marvell OCTEON CN9K and CN10K** RVU H/W block,
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packet flow and procedure to build DPDK on OCTEON cnxk platform.
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More information about CN9K and CN10K SoC can be found at `Marvell Official Website
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<https://www.marvell.com/embedded-processors/infrastructure-processors/>`_.
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Supported OCTEON cnxk SoCs
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--------------------------
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- CN93xx
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- CN96xx
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- CN98xx
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- CN106xx
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- CNF105xx
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- CN103XX
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Resource Virtualization Unit architecture
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-----------------------------------------
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The :numref:`figure_cnxk_resource_virtualization` diagram depicts the
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RVU architecture and a resource provisioning example.
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.. _figure_cnxk_resource_virtualization:
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.. figure:: img/cnxk_resource_virtualization.*
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cnxk Resource virtualization architecture and provisioning example
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Resource Virtualization Unit (RVU) on Marvell's OCTEON CN9K/CN10K SoC maps HW
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resources belonging to the network, crypto and other functional blocks onto
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PCI-compatible physical and virtual functions.
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Each functional block has multiple local functions (LFs) for
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provisioning to different PCIe devices. RVU supports multiple PCIe SRIOV
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physical functions (PFs) and virtual functions (VFs).
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The :numref:`table_cnxk_rvu_dpdk_mapping` shows the various local
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functions (LFs) provided by the RVU and its functional mapping to
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DPDK subsystem.
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.. _table_cnxk_rvu_dpdk_mapping:
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.. table:: RVU managed functional blocks and its mapping to DPDK subsystem
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+---+-----+--------------------------------------------------------------+
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| # | LF | DPDK subsystem mapping |
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+===+=====+==============================================================+
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| 1 | NIX | rte_ethdev, rte_tm, rte_event_eth_[rt]x_adapter, rte_security|
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+---+-----+--------------------------------------------------------------+
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| 2 | NPA | rte_mempool |
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+---+-----+--------------------------------------------------------------+
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| 3 | NPC | rte_flow |
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+---+-----+--------------------------------------------------------------+
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| 4 | CPT | rte_cryptodev, rte_event_crypto_adapter |
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+---+-----+--------------------------------------------------------------+
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| 5 | SSO | rte_eventdev |
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+---+-----+--------------------------------------------------------------+
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| 6 | TIM | rte_event_timer_adapter |
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+---+-----+--------------------------------------------------------------+
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| 7 | LBK | rte_ethdev |
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+---+-----+--------------------------------------------------------------+
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| 8 | DPI | rte_dmadev |
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+---+-----+--------------------------------------------------------------+
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| 9 | SDP | rte_ethdev |
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+---+-----+--------------------------------------------------------------+
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| 10| REE | rte_regexdev |
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+---+-----+--------------------------------------------------------------+
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| 11| BPHY| rte_rawdev |
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+---+-----+--------------------------------------------------------------+
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| 12| GPIO| rte_rawdev |
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+---+-----+--------------------------------------------------------------+
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PF0 is called the administrative / admin function (AF) and has exclusive
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privileges to provision RVU functional block's LFs to each of the PF/VF.
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PF/VFs communicates with AF via a shared memory region (mailbox).Upon receiving
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requests from PF/VF, AF does resource provisioning and other HW configuration.
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AF is always attached to host, but PF/VFs may be used by host kernel itself,
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or attached to VMs or to userspace applications like DPDK, etc. So, AF has to
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handle provisioning/configuration requests sent by any device from any domain.
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The AF driver does not receive or process any data.
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It is only a configuration driver used in control path.
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The :numref:`figure_cnxk_resource_virtualization` diagram also shows a
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resource provisioning example where,
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1. PFx and PFx-VF0 bound to Linux netdev driver.
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2. PFx-VF1 ethdev driver bound to the first DPDK application.
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3. PFy ethdev driver, PFy-VF0 ethdev driver, PFz eventdev driver, PFm-VF0 cryptodev driver bound to the second DPDK application.
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LBK HW Access
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-------------
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Loopback HW Unit (LBK) receives packets from NIX-RX and sends packets back to NIX-TX.
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The loopback block has N channels and contains data buffering that is shared across
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all channels. The LBK HW Unit is abstracted using ethdev subsystem, Where PF0's
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VFs are exposed as ethdev device and odd-even pairs of VFs are tied together,
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that is, packets sent on odd VF end up received on even VF and vice versa.
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This would enable HW accelerated means of communication between two domains
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where even VF bound to the first domain and odd VF bound to the second domain.
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Typical application usage models are,
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#. Communication between the Linux kernel and DPDK application.
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#. Exception path to Linux kernel from DPDK application as SW ``KNI`` replacement.
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#. Communication between two different DPDK applications.
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SDP interface
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-------------
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System DPI Packet Interface unit(SDP) provides PCIe endpoint support for remote host
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to DMA packets into and out of cnxk SoC. SDP interface comes in to live only when
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cnxk SoC is connected in PCIe endpoint mode. It can be used to send/receive
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packets to/from remote host machine using input/output queue pairs exposed to it.
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SDP interface receives input packets from remote host from NIX-RX and sends packets
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to remote host using NIX-TX. Remote host machine need to use corresponding driver
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(kernel/user mode) to communicate with SDP interface on cnxk SoC. SDP supports
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single PCIe SRIOV physical function(PF) and multiple virtual functions(VF's). Users
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can bind PF or VF to use SDP interface and it will be enumerated as ethdev ports.
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The primary use case for SDP is to enable the smart NIC use case. Typical usage models are,
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#. Communication channel between remote host and cnxk SoC over PCIe.
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#. Transfer packets received from network interface to remote host over PCIe and
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vice-versa.
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cnxk packet flow
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----------------------
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The :numref:`figure_cnxk_packet_flow_hw_accelerators` diagram depicts
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the packet flow on cnxk SoC in conjunction with use of various HW accelerators.
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.. _figure_cnxk_packet_flow_hw_accelerators:
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.. figure:: img/cnxk_packet_flow_hw_accelerators.*
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cnxk packet flow in conjunction with use of HW accelerators
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HW Offload Drivers
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------------------
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This section lists dataplane H/W block(s) available in cnxk SoC.
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#. **Ethdev Driver**
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See :doc:`../nics/cnxk` for NIX Ethdev driver information.
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#. **Mempool Driver**
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See :doc:`../mempool/cnxk` for NPA mempool driver information.
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#. **Baseband PHY Driver**
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See :doc:`../rawdevs/cnxk_bphy` for Baseband PHY driver information.
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#. **Dmadev Driver**
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See :doc:`../dmadevs/cnxk` for DPI Dmadev driver information.
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#. **Regex Device Driver**
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See :doc:`../regexdevs/cn9k` for REE Regex device driver information.
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Procedure to Setup Platform
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---------------------------
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There are three main prerequisites for setting up DPDK on cnxk
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compatible board:
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1. **RVU AF Linux kernel driver**
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The dependent kernel drivers can be obtained from the
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`kernel.org <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/ethernet/marvell/octeontx2>`_.
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Alternatively, the Marvell SDK also provides the required kernel drivers.
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Linux kernel should be configured with the following features enabled:
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.. code-block:: console
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# 64K pages enabled for better performance
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CONFIG_ARM64_64K_PAGES=y
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CONFIG_ARM64_VA_BITS_48=y
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# huge pages support enabled
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CONFIG_HUGETLBFS=y
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CONFIG_HUGETLB_PAGE=y
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# VFIO enabled with TYPE1 IOMMU at minimum
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CONFIG_VFIO_IOMMU_TYPE1=y
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CONFIG_VFIO_VIRQFD=y
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CONFIG_VFIO=y
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CONFIG_VFIO_NOIOMMU=y
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CONFIG_VFIO_PCI=y
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CONFIG_VFIO_PCI_MMAP=y
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# SMMUv3 driver
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CONFIG_ARM_SMMU_V3=y
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# ARMv8.1 LSE atomics
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CONFIG_ARM64_LSE_ATOMICS=y
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# OCTEONTX2 drivers
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CONFIG_OCTEONTX2_MBOX=y
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CONFIG_OCTEONTX2_AF=y
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# Enable if netdev PF driver required
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CONFIG_OCTEONTX2_PF=y
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# Enable if netdev VF driver required
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CONFIG_OCTEONTX2_VF=y
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CONFIG_CRYPTO_DEV_OCTEONTX2_CPT=y
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# Enable if OCTEONTX2 DMA PF driver required
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CONFIG_OCTEONTX2_DPI_PF=n
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2. **ARM64 Linux Tool Chain**
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For example, the *aarch64* Linaro Toolchain, which can be obtained from
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`here <https://releases.linaro.org/components/toolchain/binaries/7.4-2019.02/aarch64-linux-gnu/>`_.
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Alternatively, the Marvell SDK also provides GNU GCC toolchain, which is
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optimized for cnxk CPU.
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3. **Rootfile system**
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Any *aarch64* supporting filesystem may be used. For example,
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Ubuntu 15.10 (Wily) or 16.04 LTS (Xenial) userland which can be obtained
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from `<http://cdimage.ubuntu.com/ubuntu-base/releases/16.04/release/ubuntu-base-16.04.1-base-arm64.tar.gz>`_.
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Alternatively, the Marvell SDK provides the buildroot based root filesystem.
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The SDK includes all the above prerequisites necessary to bring up the cnxk board.
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- Follow the DPDK :doc:`../linux_gsg/index` to setup the basic DPDK environment.
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Debugging Options
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-----------------
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.. _table_cnxk_common_debug_options:
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.. table:: cnxk common debug options
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+---+------------+-------------------------------------------------------+
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| # | Component | EAL log command |
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+===+============+=======================================================+
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| 1 | Common | --log-level='pmd\.cnxk\.base,8' |
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+---+------------+-------------------------------------------------------+
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| 2 | Mailbox | --log-level='pmd\.cnxk\.mbox,8' |
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+---+------------+-------------------------------------------------------+
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Debugfs support
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~~~~~~~~~~~~~~~
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The **RVU AF Linux kernel driver** provides support to dump RVU blocks
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context or stats using debugfs.
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Enable ``debugfs`` by:
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1. Compile kernel with debugfs enabled, i.e ``CONFIG_DEBUGFS=y``.
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2. Boot OCTEON CN9K/CN10K with debugfs supported kernel.
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3. Verify ``debugfs`` mounted by default "mount | grep -i debugfs" or mount it manually by using.
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.. code-block:: console
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# mount -t debugfs none /sys/kernel/debug
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Currently ``debugfs`` supports the following RVU blocks NIX, NPA, NPC, NDC,
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SSO & RPM.
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The file structure under ``/sys/kernel/debug`` is as follows
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.. code-block:: console
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octeontx2/
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cn10k/
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|-- rpm
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| |-- rpm0
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| | '-- lmac0
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| | '-- stats
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| |-- rpm1
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| | |-- lmac0
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| | | '-- stats
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| | '-- lmac1
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| | '-- stats
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| '-- rpm2
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| '-- lmac0
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| '-- stats
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|-- cpt
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| |-- cpt_engines_info
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| |-- cpt_engines_sts
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| |-- cpt_err_info
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| |-- cpt_lfs_info
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| '-- cpt_pc
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|---- nix
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| |-- cq_ctx
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| |-- ndc_rx_cache
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| |-- ndc_rx_hits_miss
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| |-- ndc_tx_cache
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| |-- ndc_tx_hits_miss
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| |-- qsize
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| |-- rq_ctx
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| '-- sq_ctx
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|-- npa
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| |-- aura_ctx
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| |-- ndc_cache
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| |-- ndc_hits_miss
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| |-- pool_ctx
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| '-- qsize
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|-- npc
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| |-- mcam_info
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| |-- mcam_rules
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| '-- rx_miss_act_stats
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|-- rsrc_alloc
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'-- sso
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|-- hws
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| '-- sso_hws_info
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'-- hwgrp
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|-- sso_hwgrp_aq_thresh
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|-- sso_hwgrp_iaq_walk
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|-- sso_hwgrp_pc
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|-- sso_hwgrp_free_list_walk
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|-- sso_hwgrp_ient_walk
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'-- sso_hwgrp_taq_walk
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RVU block LF allocation:
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.. code-block:: console
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cat /sys/kernel/debug/cn10k/rsrc_alloc
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pcifunc NPA NIX SSO GROUP SSOWS TIM CPT
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PF1 0 0
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PF4 1
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PF13 0, 1 0, 1 0
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RPM example usage:
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.. code-block:: console
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cat /sys/kernel/debug/cn10k/rpm/rpm0/lmac0/stats
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=======Link Status======
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Link is UP 25000 Mbps
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=======NIX RX_STATS(rpm port level)======
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rx_ucast_frames: 0
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rx_mcast_frames: 0
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rx_bcast_frames: 0
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rx_frames: 0
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rx_bytes: 0
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rx_drops: 0
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rx_errors: 0
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=======NIX TX_STATS(rpm port level)======
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tx_ucast_frames: 0
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tx_mcast_frames: 0
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tx_bcast_frames: 0
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tx_frames: 0
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tx_bytes: 0
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tx_drops: 0
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=======rpm RX_STATS======
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Octets of received packets: 0
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Octets of received packets with out error: 0
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Received packets with alignment errors: 0
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Control/PAUSE packets received: 0
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Packets received with Frame too long Errors: 0
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Packets received with a1nrange length Errors: 0
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Received packets: 0
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Packets received with FrameCheckSequenceErrors: 0
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Packets received with VLAN header: 0
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Error packets: 0
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Packets received with unicast DMAC: 0
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Packets received with multicast DMAC: 0
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Packets received with broadcast DMAC: 0
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Dropped packets: 0
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Total frames received on interface: 0
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Packets received with an octet count < 64: 0
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Packets received with an octet count == 64: 0
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Packets received with an octet count of 65–127: 0
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Packets received with an octet count of 128-255: 0
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Packets received with an octet count of 256-511: 0
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Packets received with an octet count of 512-1023: 0
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Packets received with an octet count of 1024-1518: 0
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Packets received with an octet count of > 1518: 0
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Oversized Packets: 0
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Jabber Packets: 0
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Fragmented Packets: 0
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CBFC(class based flow control) pause frames received for class 0: 0
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CBFC pause frames received for class 1: 0
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CBFC pause frames received for class 2: 0
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CBFC pause frames received for class 3: 0
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CBFC pause frames received for class 4: 0
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CBFC pause frames received for class 5: 0
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CBFC pause frames received for class 6: 0
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CBFC pause frames received for class 7: 0
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CBFC pause frames received for class 8: 0
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CBFC pause frames received for class 9: 0
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CBFC pause frames received for class 10: 0
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CBFC pause frames received for class 11: 0
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CBFC pause frames received for class 12: 0
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CBFC pause frames received for class 13: 0
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CBFC pause frames received for class 14: 0
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CBFC pause frames received for class 15: 0
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MAC control packets received: 0
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=======rpm TX_STATS======
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Total octets sent on the interface: 0
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Total octets transmitted OK: 0
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Control/Pause frames sent: 0
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Total frames transmitted OK: 0
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Total frames sent with VLAN header: 0
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Error Packets: 0
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Packets sent to unicast DMAC: 0
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Packets sent to the multicast DMAC: 0
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Packets sent to a broadcast DMAC: 0
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Packets sent with an octet count == 64: 0
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Packets sent with an octet count of 65–127: 0
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Packets sent with an octet count of 128-255: 0
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Packets sent with an octet count of 256-511: 0
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Packets sent with an octet count of 512-1023: 0
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Packets sent with an octet count of 1024-1518: 0
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Packets sent with an octet count of > 1518: 0
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CBFC(class based flow control) pause frames transmitted for class 0: 0
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CBFC pause frames transmitted for class 1: 0
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CBFC pause frames transmitted for class 2: 0
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CBFC pause frames transmitted for class 3: 0
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CBFC pause frames transmitted for class 4: 0
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CBFC pause frames transmitted for class 5: 0
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CBFC pause frames transmitted for class 6: 0
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CBFC pause frames transmitted for class 7: 0
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CBFC pause frames transmitted for class 8: 0
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CBFC pause frames transmitted for class 9: 0
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CBFC pause frames transmitted for class 10: 0
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CBFC pause frames transmitted for class 11: 0
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CBFC pause frames transmitted for class 12: 0
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CBFC pause frames transmitted for class 13: 0
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CBFC pause frames transmitted for class 14: 0
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CBFC pause frames transmitted for class 15: 0
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MAC control packets sent: 0
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Total frames sent on the interface: 0
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CPT example usage:
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.. code-block:: console
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cat /sys/kernel/debug/cn10k/cpt/cpt_pc
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CPT instruction requests 0
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CPT instruction latency 0
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CPT NCB read requests 0
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CPT NCB read latency 0
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CPT read requests caused by UC fills 0
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CPT active cycles pc 1395642
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CPT clock count pc 5579867595493
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NIX example usage:
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.. code-block:: console
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Usage: echo <nixlf> [cq number/all] > /sys/kernel/debug/cn10k/nix/cq_ctx
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cat /sys/kernel/debug/cn10k/nix/cq_ctx
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echo 0 0 > /sys/kernel/debug/cn10k/nix/cq_ctx
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cat /sys/kernel/debug/cn10k/nix/cq_ctx
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=====cq_ctx for nixlf:0 and qidx:0 is=====
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W0: base 158ef1a00
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W1: wrptr 0
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W1: avg_con 0
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W1: cint_idx 0
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W1: cq_err 0
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W1: qint_idx 0
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W1: bpid 0
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W1: bp_ena 0
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W2: update_time 31043
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W2:avg_level 255
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W2: head 0
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W2:tail 0
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W3: cq_err_int_ena 5
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W3:cq_err_int 0
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W3: qsize 4
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W3:caching 1
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W3: substream 0x000
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W3: ena 1
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W3: drop_ena 1
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W3: drop 64
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W3: bp 0
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NPA example usage:
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.. code-block:: console
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Usage: echo <npalf> [pool number/all] > /sys/kernel/debug/cn10k/npa/pool_ctx
|
||
cat /sys/kernel/debug/cn10k/npa/pool_ctx
|
||
echo 0 0 > /sys/kernel/debug/cn10k/npa/pool_ctx
|
||
cat /sys/kernel/debug/cn10k/npa/pool_ctx
|
||
|
||
======POOL : 0=======
|
||
W0: Stack base 1375bff00
|
||
W1: ena 1
|
||
W1: nat_align 1
|
||
W1: stack_caching 1
|
||
W1: stack_way_mask 0
|
||
W1: buf_offset 1
|
||
W1: buf_size 19
|
||
W2: stack_max_pages 24315
|
||
W2: stack_pages 24314
|
||
W3: op_pc 267456
|
||
W4: stack_offset 2
|
||
W4: shift 5
|
||
W4: avg_level 255
|
||
W4: avg_con 0
|
||
W4: fc_ena 0
|
||
W4: fc_stype 0
|
||
W4: fc_hyst_bits 0
|
||
W4: fc_up_crossing 0
|
||
W4: update_time 62993
|
||
W5: fc_addr 0
|
||
W6: ptr_start 1593adf00
|
||
W7: ptr_end 180000000
|
||
W8: err_int 0
|
||
W8: err_int_ena 7
|
||
W8: thresh_int 0
|
||
W8: thresh_int_ena 0
|
||
W8: thresh_up 0
|
||
W8: thresh_qint_idx 0
|
||
W8: err_qint_idx 0
|
||
|
||
NPC example usage:
|
||
|
||
.. code-block:: console
|
||
|
||
cat /sys/kernel/debug/cn10k/npc/mcam_info
|
||
|
||
NPC MCAM info:
|
||
RX keywidth : 224bits
|
||
TX keywidth : 224bits
|
||
|
||
MCAM entries : 2048
|
||
Reserved : 158
|
||
Available : 1890
|
||
|
||
MCAM counters : 512
|
||
Reserved : 1
|
||
Available : 511
|
||
|
||
SSO example usage:
|
||
|
||
.. code-block:: console
|
||
|
||
Usage: echo [<hws>/all] > /sys/kernel/debug/cn10k/sso/hws/sso_hws_info
|
||
echo 0 > /sys/kernel/debug/cn10k/sso/hws/sso_hws_info
|
||
|
||
==================================================
|
||
SSOW HWS[0] Arbitration State 0x0
|
||
SSOW HWS[0] Guest Machine Control 0x0
|
||
SSOW HWS[0] SET[0] Group Mask[0] 0xffffffffffffffff
|
||
SSOW HWS[0] SET[0] Group Mask[1] 0xffffffffffffffff
|
||
SSOW HWS[0] SET[0] Group Mask[2] 0xffffffffffffffff
|
||
SSOW HWS[0] SET[0] Group Mask[3] 0xffffffffffffffff
|
||
SSOW HWS[0] SET[1] Group Mask[0] 0xffffffffffffffff
|
||
SSOW HWS[0] SET[1] Group Mask[1] 0xffffffffffffffff
|
||
SSOW HWS[0] SET[1] Group Mask[2] 0xffffffffffffffff
|
||
SSOW HWS[0] SET[1] Group Mask[3] 0xffffffffffffffff
|
||
==================================================
|
||
|
||
Compile DPDK
|
||
------------
|
||
|
||
DPDK may be compiled either natively on OCTEON CN9K/CN10K platform or cross-compiled on
|
||
an x86 based platform.
|
||
|
||
Native Compilation
|
||
~~~~~~~~~~~~~~~~~~
|
||
|
||
Refer to :doc:`../linux_gsg/build_dpdk` for generic native builds.
|
||
|
||
CN9K:
|
||
|
||
.. code-block:: console
|
||
|
||
meson -Dplatform=cn9k build
|
||
ninja -C build
|
||
|
||
CN10K:
|
||
|
||
.. code-block:: console
|
||
|
||
meson -Dplatform=cn10k build
|
||
ninja -C build
|
||
|
||
Cross Compilation
|
||
~~~~~~~~~~~~~~~~~
|
||
|
||
Refer to :doc:`../linux_gsg/cross_build_dpdk_for_arm64` for generic arm64 details.
|
||
|
||
CN9K:
|
||
|
||
.. code-block:: console
|
||
|
||
meson build --cross-file config/arm/arm64_cn9k_linux_gcc
|
||
ninja -C build
|
||
|
||
CN10K:
|
||
|
||
.. code-block:: console
|
||
|
||
meson build --cross-file config/arm/arm64_cn10k_linux_gcc
|
||
ninja -C build
|
||
|
||
.. note::
|
||
|
||
By default, meson cross compilation uses ``aarch64-linux-gnu-gcc`` toolchain,
|
||
if Marvell toolchain is available then it can be used by overriding the
|
||
c, cpp, ar, strip ``binaries`` attributes to respective Marvell
|
||
toolchain binaries in ``config/arm/arm64_cn10k_linux_gcc`` file.
|
||
|
||
Environment Variables
|
||
~~~~~~~~~~~~~~~~~~~~~
|
||
|
||
* ``BPHY_INTR_MLOCK_DISABLE``
|
||
When defined disables memory locking in
|
||
BPHY environment.
|
||
|
||
* ``ROC_CN10K_MBOX_TIMEOUT``, ``ROC_MBOX_TIMEOUT``
|
||
When set, overrides MBOX timeout by value in milli seconds.
|
||
|
||
* ``ETH_SEC_IV_OVR``
|
||
When set, overrides outbound inline SA IV. By default IV is generated
|
||
by HW. Format of variable is string of comma separated one byte values as
|
||
for ex: "0x0, 0x10, 0x20, ..."
|