e4b73bee79
When the MSB is not set, the lower 11 bits do not represent bytes, but
chunks of 64 bytes. Adjust the rate limit burst size calculation
accordingly, and update the comments to indicate the way the hardware
actually works.
Fixes: 93e84b1bfc92 ("net/ice/base: add basic Tx scheduler")
Cc: stable@dpdk.org
Signed-off-by: Ben Shelton <benjamin.h.shelton@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Leyi Rong <leyi.rong@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
189 lines
7.0 KiB
C
189 lines
7.0 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2001-2019
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*/
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#ifndef _ICE_SCHED_H_
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#define _ICE_SCHED_H_
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#include "ice_common.h"
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#define ICE_QGRP_LAYER_OFFSET 2
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#define ICE_VSI_LAYER_OFFSET 4
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#define ICE_AGG_LAYER_OFFSET 6
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#define ICE_SCHED_INVAL_LAYER_NUM 0xFF
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/* Burst size is a 12 bits register that is configured while creating the RL
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* profile(s). MSB is a granularity bit and tells the granularity type
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* 0 - LSB bits are in 64 bytes granularity
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* 1 - LSB bits are in 1K bytes granularity
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*/
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#define ICE_64_BYTE_GRANULARITY 0
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#define ICE_KBYTE_GRANULARITY BIT(11)
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#define ICE_MIN_BURST_SIZE_ALLOWED 64 /* In Bytes */
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#define ICE_MAX_BURST_SIZE_ALLOWED \
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((BIT(11) - 1) * 1024) /* In Bytes */
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#define ICE_MAX_BURST_SIZE_64_BYTE_GRANULARITY \
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((BIT(11) - 1) * 64) /* In Bytes */
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#define ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY ICE_MAX_BURST_SIZE_ALLOWED
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#define ICE_RL_PROF_FREQUENCY 446000000
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#define ICE_RL_PROF_ACCURACY_BYTES 128
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#define ICE_RL_PROF_MULTIPLIER 10000
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#define ICE_RL_PROF_TS_MULTIPLIER 32
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#define ICE_RL_PROF_FRACTION 512
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struct rl_profile_params {
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u32 bw; /* in Kbps */
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u16 rl_multiplier;
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u16 wake_up_calc;
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u16 rl_encode;
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};
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/* BW rate limit profile parameters list entry along
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* with bandwidth maintained per layer in port info
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*/
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struct ice_aqc_rl_profile_info {
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struct ice_aqc_rl_profile_elem profile;
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struct LIST_ENTRY_TYPE list_entry;
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u32 bw; /* requested */
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u16 prof_id_ref; /* profile ID to node association ref count */
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};
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struct ice_sched_agg_vsi_info {
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struct LIST_ENTRY_TYPE list_entry;
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ice_declare_bitmap(tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
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u16 vsi_handle;
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/* save aggregator VSI TC bitmap */
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ice_declare_bitmap(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
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};
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struct ice_sched_agg_info {
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struct LIST_HEAD_TYPE agg_vsi_list;
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struct LIST_ENTRY_TYPE list_entry;
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ice_declare_bitmap(tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
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u32 agg_id;
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enum ice_agg_type agg_type;
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/* bw_t_info saves aggregator BW information */
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struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
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/* save aggregator TC bitmap */
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ice_declare_bitmap(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
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};
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/* FW AQ command calls */
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enum ice_status
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ice_aq_query_rl_profile(struct ice_hw *hw, u16 num_profiles,
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struct ice_aqc_rl_profile_generic_elem *buf,
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u16 buf_size, struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_cfg_l2_node_cgd(struct ice_hw *hw, u16 num_nodes,
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struct ice_aqc_cfg_l2_node_cgd_data *buf, u16 buf_size,
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struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req,
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struct ice_aqc_get_elem *buf, u16 buf_size,
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u16 *elems_ret, struct ice_sq_cd *cd);
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enum ice_status ice_sched_init_port(struct ice_port_info *pi);
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enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw);
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/* Functions to cleanup scheduler SW DB */
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void ice_sched_clear_port(struct ice_port_info *pi);
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void ice_sched_cleanup_all(struct ice_hw *hw);
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void ice_sched_clear_agg(struct ice_hw *hw);
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/* Get a scheduling node from SW DB for given TEID */
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struct ice_sched_node *ice_sched_get_node(struct ice_port_info *pi, u32 teid);
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struct ice_sched_node *
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ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid);
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/* Add a scheduling node into SW DB for given info */
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enum ice_status
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ice_sched_add_node(struct ice_port_info *pi, u8 layer,
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struct ice_aqc_txsched_elem_data *info);
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void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node);
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struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc);
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struct ice_sched_node *
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ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
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u8 owner);
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enum ice_status
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ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs,
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u8 owner, bool enable);
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enum ice_status ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle);
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struct ice_sched_node *
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ice_sched_get_vsi_node(struct ice_hw *hw, struct ice_sched_node *tc_node,
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u16 vsi_handle);
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bool ice_sched_is_tree_balanced(struct ice_hw *hw, struct ice_sched_node *node);
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enum ice_status
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ice_aq_query_node_to_root(struct ice_hw *hw, u32 node_teid,
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struct ice_aqc_get_elem *buf, u16 buf_size,
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struct ice_sq_cd *cd);
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/* Tx scheduler rate limiter functions */
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enum ice_status
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ice_cfg_agg(struct ice_port_info *pi, u32 agg_id,
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enum ice_agg_type agg_type, u8 tc_bitmap);
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enum ice_status
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ice_move_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle,
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u8 tc_bitmap);
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enum ice_status ice_rm_agg_cfg(struct ice_port_info *pi, u32 agg_id);
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enum ice_status
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ice_cfg_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
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u16 q_handle, enum ice_rl_type rl_type, u32 bw);
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enum ice_status
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ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
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u16 q_handle, enum ice_rl_type rl_type);
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enum ice_status
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ice_cfg_tc_node_bw_lmt(struct ice_port_info *pi, u8 tc,
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enum ice_rl_type rl_type, u32 bw);
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enum ice_status
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ice_cfg_tc_node_bw_dflt_lmt(struct ice_port_info *pi, u8 tc,
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enum ice_rl_type rl_type);
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enum ice_status
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ice_cfg_vsi_bw_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
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enum ice_rl_type rl_type, u32 bw);
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enum ice_status
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ice_cfg_vsi_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
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enum ice_rl_type rl_type);
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enum ice_status
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ice_cfg_agg_bw_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc,
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enum ice_rl_type rl_type, u32 bw);
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enum ice_status
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ice_cfg_agg_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc,
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enum ice_rl_type rl_type);
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enum ice_status
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ice_cfg_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle, u32 bw);
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enum ice_status
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ice_cfg_vsi_bw_no_shared_lmt(struct ice_port_info *pi, u16 vsi_handle);
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enum ice_status
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ice_cfg_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw);
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enum ice_status
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ice_cfg_agg_bw_no_shared_lmt(struct ice_port_info *pi, u32 agg_id);
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enum ice_status
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ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids,
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u8 *q_prio);
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enum ice_status
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ice_cfg_vsi_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 ena_tcmap,
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enum ice_rl_type rl_type, u8 *bw_alloc);
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enum ice_status
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ice_cfg_agg_vsi_priority_per_tc(struct ice_port_info *pi, u32 agg_id,
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u16 num_vsis, u16 *vsi_handle_arr,
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u8 *node_prio, u8 tc);
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enum ice_status
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ice_cfg_agg_bw_alloc(struct ice_port_info *pi, u32 agg_id, u8 ena_tcmap,
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enum ice_rl_type rl_type, u8 *bw_alloc);
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bool
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ice_sched_find_node_in_subtree(struct ice_hw *hw, struct ice_sched_node *base,
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struct ice_sched_node *node);
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enum ice_status
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ice_sched_set_agg_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle);
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enum ice_status
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ice_sched_set_node_bw_lmt_per_tc(struct ice_port_info *pi, u32 id,
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enum ice_agg_type agg_type, u8 tc,
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enum ice_rl_type rl_type, u32 bw);
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enum ice_status
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ice_sched_set_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle,
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u32 bw);
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enum ice_status
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ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw);
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enum ice_status
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ice_sched_cfg_sibl_node_prio(struct ice_hw *hw, struct ice_sched_node *node,
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u8 priority);
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#endif /* _ICE_SCHED_H_ */
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