ec94dbc573
The base driver is the backend module for the QLogic FastLinQ QL4xxxx 25G/40G CNA family of adapters as well as their virtual functions (VF) in SR-IOV context. The purpose of the base module is to: - provide all the common code that will be shared between the various drivers that would be used with said line of products. Flows such as chip initialization and de-initialization fall under this category. - abstract the protocol-specific HW & FW components, allowing the protocol drivers to have clean APIs, which are detached in its slowpath configuration from the actual Hardware Software Interface(HSI). This patch adds a base module without any protocol-specific bits. I.e., this adds a basic implementation that almost entirely falls under the first category. Signed-off-by: Harish Patil <harish.patil@qlogic.com> Signed-off-by: Rasesh Mody <rasesh.mody@qlogic.com> Signed-off-by: Sony Chacko <sony.chacko@qlogic.com>
270 lines
6.0 KiB
C
270 lines
6.0 KiB
C
/*
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* Copyright (c) 2016 QLogic Corporation.
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* All rights reserved.
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* www.qlogic.com
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*
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* See LICENSE.qede_pmd for copyright and licensing details.
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*/
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#ifndef __ECORE_HW_H__
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#define __ECORE_HW_H__
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#include "ecore.h"
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#include "ecore_dev_api.h"
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/* Forward decleration */
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struct ecore_ptt;
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enum reserved_ptts {
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RESERVED_PTT_EDIAG,
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RESERVED_PTT_USER_SPACE,
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RESERVED_PTT_MAIN,
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RESERVED_PTT_DPC,
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RESERVED_PTT_MAX
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};
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/* @@@TMP - in earlier versions of the emulation, the HW lock started from 1
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* instead of 0, this should be fixed in later HW versions.
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*/
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#ifndef MISC_REG_DRIVER_CONTROL_0
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#define MISC_REG_DRIVER_CONTROL_0 MISC_REG_DRIVER_CONTROL_1
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#endif
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#ifndef MISC_REG_DRIVER_CONTROL_0_SIZE
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#define MISC_REG_DRIVER_CONTROL_0_SIZE MISC_REG_DRIVER_CONTROL_1_SIZE
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#endif
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enum _dmae_cmd_dst_mask {
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DMAE_CMD_DST_MASK_NONE = 0,
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DMAE_CMD_DST_MASK_PCIE = 1,
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DMAE_CMD_DST_MASK_GRC = 2
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};
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enum _dmae_cmd_src_mask {
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DMAE_CMD_SRC_MASK_PCIE = 0,
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DMAE_CMD_SRC_MASK_GRC = 1
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};
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enum _dmae_cmd_crc_mask {
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DMAE_CMD_COMP_CRC_EN_MASK_NONE = 0,
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DMAE_CMD_COMP_CRC_EN_MASK_SET = 1
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};
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/* definitions for DMA constants */
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#define DMAE_GO_VALUE 0x1
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#ifdef __BIG_ENDIAN
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#define DMAE_COMPLETION_VAL 0xAED10000
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#define DMAE_CMD_ENDIANITY 0x3
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#else
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#define DMAE_COMPLETION_VAL 0xD1AE
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#define DMAE_CMD_ENDIANITY 0x2
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#endif
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#define DMAE_CMD_SIZE 14
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/* size of DMAE command structure to fill.. DMAE_CMD_SIZE-5 */
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#define DMAE_CMD_SIZE_TO_FILL (DMAE_CMD_SIZE - 5)
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/* Minimum wait for dmae opertaion to complete 2 milliseconds */
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#define DMAE_MIN_WAIT_TIME 0x2
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#define DMAE_MAX_CLIENTS 32
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/**
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* @brief ecore_gtt_init - Initialize GTT windows
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*
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* @param p_hwfn
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*/
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void ecore_gtt_init(struct ecore_hwfn *p_hwfn);
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/**
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* @brief ecore_ptt_invalidate - Forces all ptt entries to be re-configured
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*
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* @param p_hwfn
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*/
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void ecore_ptt_invalidate(struct ecore_hwfn *p_hwfn);
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/**
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* @brief ecore_ptt_pool_alloc - Allocate and initialize PTT pool
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*
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* @param p_hwfn
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*
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* @return _ecore_status_t - success (0), negative - error.
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*/
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enum _ecore_status_t ecore_ptt_pool_alloc(struct ecore_hwfn *p_hwfn);
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/**
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* @brief ecore_ptt_pool_free -
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*
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* @param p_hwfn
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*/
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void ecore_ptt_pool_free(struct ecore_hwfn *p_hwfn);
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/**
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* @brief ecore_ptt_get_hw_addr - Get PTT's GRC/HW address
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*
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* @param p_hwfn
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* @param p_ptt
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*
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* @return u32
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*/
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u32 ecore_ptt_get_hw_addr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
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/**
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* @brief ecore_ptt_get_bar_addr - Get PPT's external BAR address
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*
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* @param p_hwfn
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* @param p_ptt
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*
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* @return u32
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*/
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u32 ecore_ptt_get_bar_addr(struct ecore_ptt *p_ptt);
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/**
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* @brief ecore_ptt_set_win - Set PTT Window's GRC BAR address
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*
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* @param p_hwfn
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* @param new_hw_addr
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* @param p_ptt
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*/
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void ecore_ptt_set_win(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt, u32 new_hw_addr);
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/**
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* @brief ecore_get_reserved_ptt - Get a specific reserved PTT
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*
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* @param p_hwfn
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* @param ptt_idx
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*
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* @return struct ecore_ptt *
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*/
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struct ecore_ptt *ecore_get_reserved_ptt(struct ecore_hwfn *p_hwfn,
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enum reserved_ptts ptt_idx);
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/**
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* @brief ecore_wr - Write value to BAR using the given ptt
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*
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* @param p_hwfn
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* @param p_ptt
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* @param val
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* @param hw_addr
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*/
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void ecore_wr(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt, u32 hw_addr, u32 val);
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/**
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* @brief ecore_rd - Read value from BAR using the given ptt
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*
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* @param p_hwfn
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* @param p_ptt
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* @param val
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* @param hw_addr
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*/
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u32 ecore_rd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 hw_addr);
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/**
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* @brief ecore_memcpy_from - copy n bytes from BAR using the given
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* ptt
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*
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* @param p_hwfn
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* @param p_ptt
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* @param dest
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* @param hw_addr
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* @param n
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*/
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void ecore_memcpy_from(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt,
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void *dest, u32 hw_addr, osal_size_t n);
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/**
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* @brief ecore_memcpy_to - copy n bytes to BAR using the given
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* ptt
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*
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* @param p_hwfn
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* @param p_ptt
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* @param hw_addr
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* @param src
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* @param n
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*/
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void ecore_memcpy_to(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt,
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u32 hw_addr, void *src, osal_size_t n);
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/**
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* @brief ecore_fid_pretend - pretend to another function when
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* accessing the ptt window. There is no way to unpretend
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* a function. The only way to cancel a pretend is to
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* pretend back to the original function.
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*
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* @param p_hwfn
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* @param p_ptt
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* @param fid - fid field of pxp_pretend structure. Can contain
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* either pf / vf, port/path fields are don't care.
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*/
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void ecore_fid_pretend(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt, u16 fid);
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/**
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* @brief ecore_port_pretend - pretend to another port when
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* accessing the ptt window
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*
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* @param p_hwfn
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* @param p_ptt
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* @param port_id - the port to pretend to
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*/
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void ecore_port_pretend(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt, u8 port_id);
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/**
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* @brief ecore_port_unpretend - cancel any previously set port
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* pretend
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*
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* @param p_hwfn
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* @param p_ptt
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*/
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void ecore_port_unpretend(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
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/**
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* @brief ecore_vfid_to_concrete - build a concrete FID for a
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* given VF ID
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*
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* @param p_hwfn
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* @param p_ptt
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* @param vfid
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*/
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u32 ecore_vfid_to_concrete(struct ecore_hwfn *p_hwfn, u8 vfid);
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/**
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* @brief ecore_dmae_info_alloc - Init the dmae_info structure
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* which is part of p_hwfn.
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* @param p_hwfn
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*/
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enum _ecore_status_t ecore_dmae_info_alloc(struct ecore_hwfn *p_hwfn);
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/**
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* @brief ecore_dmae_info_free - Free the dmae_info structure
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* which is part of p_hwfn
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*
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* @param p_hwfn
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*/
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void ecore_dmae_info_free(struct ecore_hwfn *p_hwfn);
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union ecore_qm_pq_params {
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struct {
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u8 tc;
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} core;
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struct {
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u8 is_vf;
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u8 vf_id;
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u8 tc;
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} eth;
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};
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u16 ecore_get_qm_pq(struct ecore_hwfn *p_hwfn,
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enum protocol_type proto, union ecore_qm_pq_params *params);
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enum _ecore_status_t ecore_init_fw_data(struct ecore_dev *p_dev,
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const u8 *fw_data);
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void ecore_hw_err_notify(struct ecore_hwfn *p_hwfn,
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enum ecore_hw_err_type err_type);
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#endif /* __ECORE_HW_H__ */
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