2ea6f76aff
The Qlogic Everest Driver for Ethernet(QEDE) Poll Mode Driver(PMD) is the DPDK specific module for QLogic FastLinQ QL4xxxx 25G/40G CNA family of adapters as well as their virtual functions (VF) in SR-IOV context. This patch adds QEDE PMD, which interacts with base driver and initialises the HW. This patch content also includes: - eth_dev_ops callbacks - Rx/Tx support for the driver - link default configuration - change link property - link up/down/update notifications - vlan offload and filtering capability - device/function/port statistics - qede nic guide and updated overview.rst Note that the follow on commits contain the code for the features mentioned in documents but not implemented in this patch. Signed-off-by: Harish Patil <harish.patil@qlogic.com> Signed-off-by: Rasesh Mody <rasesh.mody@qlogic.com> Signed-off-by: Sony Chacko <sony.chacko@qlogic.com>
180 lines
4.5 KiB
C
180 lines
4.5 KiB
C
/*
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* Copyright (c) 2016 QLogic Corporation.
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* All rights reserved.
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* www.qlogic.com
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*
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* See LICENSE.qede_pmd for copyright and licensing details.
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*/
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#ifndef _QEDE_RXTX_H_
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#define _QEDE_RXTX_H_
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#include "qede_ethdev.h"
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/* Ring Descriptors */
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#define RX_RING_SIZE_POW 16 /* 64K */
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#define RX_RING_SIZE (1ULL << RX_RING_SIZE_POW)
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#define NUM_RX_BDS_MAX (RX_RING_SIZE - 1)
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#define NUM_RX_BDS_MIN 128
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#define NUM_RX_BDS_DEF NUM_RX_BDS_MAX
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#define NUM_RX_BDS(q) (q->nb_rx_desc - 1)
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#define TX_RING_SIZE_POW 16 /* 64K */
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#define TX_RING_SIZE (1ULL << TX_RING_SIZE_POW)
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#define NUM_TX_BDS_MAX (TX_RING_SIZE - 1)
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#define NUM_TX_BDS_MIN 128
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#define NUM_TX_BDS_DEF NUM_TX_BDS_MAX
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#define NUM_TX_BDS(q) (q->nb_tx_desc - 1)
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#define TX_CONS(txq) (txq->sw_tx_cons & NUM_TX_BDS(txq))
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#define TX_PROD(txq) (txq->sw_tx_prod & NUM_TX_BDS(txq))
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/* Number of TX BDs per packet used currently */
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#define MAX_NUM_TX_BDS 1
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#define QEDE_DEFAULT_TX_FREE_THRESH 32
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#define QEDE_CSUM_ERROR (1 << 0)
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#define QEDE_CSUM_UNNECESSARY (1 << 1)
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#define QEDE_TUNN_CSUM_UNNECESSARY (1 << 2)
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#define QEDE_BD_SET_ADDR_LEN(bd, maddr, len) \
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do { \
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(bd)->addr.hi = rte_cpu_to_le_32(U64_HI(maddr)); \
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(bd)->addr.lo = rte_cpu_to_le_32(U64_LO(maddr)); \
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(bd)->nbytes = rte_cpu_to_le_16(len); \
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} while (0)
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#define CQE_HAS_VLAN(flags) \
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((flags) & (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK \
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<< PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT))
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#define CQE_HAS_OUTER_VLAN(flags) \
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((flags) & (PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK \
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<< PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT))
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/* Max supported alignment is 256 (8 shift)
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* minimal alignment shift 6 is optimal for 57xxx HW performance
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*/
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#define QEDE_L1_CACHE_SHIFT 6
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#define QEDE_RX_ALIGN_SHIFT (RTE_MAX(6, RTE_MIN(8, QEDE_L1_CACHE_SHIFT)))
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#define QEDE_FW_RX_ALIGN_END (1UL << QEDE_RX_ALIGN_SHIFT)
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#define QEDE_ETH_OVERHEAD (ETHER_HDR_LEN + 8 + 8 + QEDE_FW_RX_ALIGN_END)
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/* TBD: Excluding IPV6 */
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#define QEDE_RSS_OFFLOAD_ALL (ETH_RSS_IPV4 | ETH_RSS_NONFRAG_IPV4_TCP | \
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ETH_RSS_NONFRAG_IPV4_UDP)
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#define QEDE_TXQ_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS)
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#define MAX_NUM_TC 8
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#define for_each_rss(i) for (i = 0; i < qdev->num_rss; i++)
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/*
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* RX BD descriptor ring
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*/
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struct qede_rx_entry {
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struct rte_mbuf *mbuf;
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uint32_t page_offset;
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/* allows expansion .. */
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};
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/*
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* Structure associated with each RX queue.
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*/
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struct qede_rx_queue {
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struct rte_mempool *mb_pool;
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struct ecore_chain rx_bd_ring;
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struct ecore_chain rx_comp_ring;
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uint16_t *hw_cons_ptr;
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void OSAL_IOMEM *hw_rxq_prod_addr;
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struct qede_rx_entry *sw_rx_ring;
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uint16_t sw_rx_cons;
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uint16_t sw_rx_prod;
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uint16_t nb_rx_desc;
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uint16_t queue_id;
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uint16_t port_id;
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uint16_t rx_buf_size;
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uint64_t rx_hw_errors;
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uint64_t rx_alloc_errors;
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struct qede_dev *qdev;
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};
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/*
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* TX BD descriptor ring
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*/
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struct qede_tx_entry {
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struct rte_mbuf *mbuf;
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uint8_t flags;
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};
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union db_prod {
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struct eth_db_data data;
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uint32_t raw;
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};
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struct qede_tx_queue {
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struct ecore_chain tx_pbl;
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struct qede_tx_entry *sw_tx_ring;
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uint16_t nb_tx_desc;
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uint16_t nb_tx_avail;
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uint16_t tx_free_thresh;
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uint16_t queue_id;
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uint16_t *hw_cons_ptr;
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uint16_t sw_tx_cons;
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uint16_t sw_tx_prod;
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void OSAL_IOMEM *doorbell_addr;
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volatile union db_prod tx_db;
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uint16_t port_id;
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uint64_t txq_counter;
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struct qede_dev *qdev;
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};
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struct qede_fastpath {
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struct qede_dev *qdev;
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uint8_t rss_id;
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struct ecore_sb_info *sb_info;
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struct qede_rx_queue *rxq;
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struct qede_tx_queue *txqs[MAX_NUM_TC];
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char name[80];
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};
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/*
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* RX/TX function prototypes
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*/
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int qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
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uint16_t nb_desc, unsigned int socket_id,
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const struct rte_eth_rxconf *rx_conf,
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struct rte_mempool *mp);
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int qede_tx_queue_setup(struct rte_eth_dev *dev,
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uint16_t queue_idx,
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uint16_t nb_desc,
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unsigned int socket_id,
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const struct rte_eth_txconf *tx_conf);
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void qede_rx_queue_release(void *rx_queue);
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void qede_tx_queue_release(void *tx_queue);
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int qede_dev_start(struct rte_eth_dev *eth_dev);
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void qede_dev_stop(struct rte_eth_dev *eth_dev);
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void qede_reset_fp_rings(struct qede_dev *qdev);
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void qede_free_fp_arrays(struct qede_dev *qdev);
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void qede_free_mem_load(struct qede_dev *qdev);
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uint16_t qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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uint16_t qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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#endif /* _QEDE_RXTX_H_ */
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