fe93968722
The name "mrvl" for Marvell PMD driver for PPv2 Marvell PPv2 (Packet Processor v2) 1/10 Gbps adapter is too generic and causes problem for adding new PMD drivers for other Marvell devices. Changed to "mvpp2" for specific Marvell PPv2 PMD. This patch doesn't introduce any change except renaming. Signed-off-by: Natalie Samsonov <nsamsono@marvell.com> Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
102 lines
2.8 KiB
C
102 lines
2.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2017 Marvell International Ltd.
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* Copyright(c) 2017 Semihalf.
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* All rights reserved.
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*/
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#ifndef _MRVL_ETHDEV_H_
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#define _MRVL_ETHDEV_H_
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#include <rte_spinlock.h>
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#include <rte_flow_driver.h>
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#include <env/mv_autogen_comp_flags.h>
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#include <drivers/mv_pp2.h>
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#include <drivers/mv_pp2_bpool.h>
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#include <drivers/mv_pp2_cls.h>
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#include <drivers/mv_pp2_hif.h>
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#include <drivers/mv_pp2_ppio.h>
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/** Maximum number of rx queues per port */
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#define MRVL_PP2_RXQ_MAX 32
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/** Maximum number of tx queues per port */
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#define MRVL_PP2_TXQ_MAX 8
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/** Minimum number of descriptors in tx queue */
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#define MRVL_PP2_TXD_MIN 16
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/** Maximum number of descriptors in tx queue */
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#define MRVL_PP2_TXD_MAX 2048
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/** Tx queue descriptors alignment */
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#define MRVL_PP2_TXD_ALIGN 16
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/** Minimum number of descriptors in rx queue */
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#define MRVL_PP2_RXD_MIN 16
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/** Maximum number of descriptors in rx queue */
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#define MRVL_PP2_RXD_MAX 2048
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/** Rx queue descriptors alignment */
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#define MRVL_PP2_RXD_ALIGN 16
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/** Maximum number of descriptors in tx aggregated queue */
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#define MRVL_PP2_AGGR_TXQD_MAX 2048
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/** Maximum number of Traffic Classes. */
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#define MRVL_PP2_TC_MAX 8
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/** Packet offset inside RX buffer. */
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#define MRVL_PKT_OFFS 64
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/** Maximum number of descriptors in shadow queue. Must be power of 2 */
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#define MRVL_PP2_TX_SHADOWQ_SIZE MRVL_PP2_TXD_MAX
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/** Shadow queue size mask (since shadow queue size is power of 2) */
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#define MRVL_PP2_TX_SHADOWQ_MASK (MRVL_PP2_TX_SHADOWQ_SIZE - 1)
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/** Minimum number of sent buffers to release from shadow queue to BM */
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#define MRVL_PP2_BUF_RELEASE_BURST_SIZE 64
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struct mrvl_priv {
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/* Hot fields, used in fast path. */
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struct pp2_bpool *bpool; /**< BPool pointer */
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struct pp2_ppio *ppio; /**< Port handler pointer */
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rte_spinlock_t lock; /**< Spinlock for checking bpool status */
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uint16_t bpool_max_size; /**< BPool maximum size */
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uint16_t bpool_min_size; /**< BPool minimum size */
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uint16_t bpool_init_size; /**< Configured BPool size */
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/** Mapping for DPDK rx queue->(TC, MRVL relative inq) */
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struct {
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uint8_t tc; /**< Traffic Class */
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uint8_t inq; /**< Relative in-queue number */
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} rxq_map[MRVL_PP2_RXQ_MAX] __rte_cache_aligned;
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/* Configuration data, used sporadically. */
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uint8_t pp_id;
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uint8_t ppio_id;
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uint8_t bpool_bit;
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uint8_t rss_hf_tcp;
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uint8_t uc_mc_flushed;
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uint8_t vlan_flushed;
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uint8_t isolated;
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struct pp2_ppio_params ppio_params;
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struct pp2_cls_qos_tbl_params qos_tbl_params;
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struct pp2_cls_tbl *qos_tbl;
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uint16_t nb_rx_queues;
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struct pp2_cls_tbl_params cls_tbl_params;
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struct pp2_cls_tbl *cls_tbl;
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uint32_t cls_tbl_pattern;
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LIST_HEAD(mrvl_flows, rte_flow) flows;
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struct pp2_cls_plcr *policer;
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};
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/** Flow operations forward declaration. */
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extern const struct rte_flow_ops mrvl_flow_ops;
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#endif /* _MRVL_ETHDEV_H_ */
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