e9b9739264
RTE_ARCH_xx flags are used to distinguish platform architectures.
These flags can be used to pick different code paths for different
architectures at compile time.
For Arm platforms, there are 3 flags in use: RTE_ARCH_ARM,
RTE_ARCH_ARMv7 and RTE_ARCH_ARM64.
RTE_ARCH_ARM64 is for 64-bit aarch64 platforms,
and RTE_ARCH_ARM & RTE_ARCH_ARMv7 are for 32-bit platforms.
RTE_ARCH_ARMv7 is for ARMv7 platforms as its name suggested.
The issue is meaning of RTE_ARCH_ARM is not clear enough.
Because no info about platform word length is included in the name.
To make the flag names more clear, a naming scheme is proposed.
RTE_ARCH_ARM (all Arm platforms)
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+----RTE_ARCH_32 (New. 32-bit platforms of all architectures)
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| +----RTE_ARCH_ARMv7 (ARMv7 platforms)
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| +----RTE_ARCH_ARMv8_AARCH32 (aarch32 state on aarch64 machine)
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+----RTE_ARCH_64 (64-bit platforms of all architectures)
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+----RTE_ARCH_ARM64 (64-bit Arm platforms)
RTE_ARCH_32 will be explicitly defined for 32-bit platforms.
To fit into the new naming scheme, current usage of RTE_ARCH_ARM in
project is mapped to (RTE_ARCH_ARM && RTE_ARCH_32).
Matching flags for other architectures are:
RTE_ARCH_X86
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+----RTE_ARCH_32
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| +----RTE_ARCH_I686
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| +----RTE_ARCH_X86_X32
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+----RTE_ARCH_64
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+----RTE_ARCH_X86_64
RTE_ARCH_PPC_64 ---- RTE_ARCH_64
Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Phil Yang <phil.yang@arm.com>
222 lines
7.2 KiB
Meson
222 lines
7.2 KiB
Meson
# SPDX-License-Identifier: BSD-3-Clause
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# Copyright(c) 2017 Intel Corporation.
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# Copyright(c) 2017 Cavium, Inc
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# for checking defines we need to use the correct compiler flags
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march_opt = '-march=@0@'.format(machine)
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arm_force_native_march = false
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arm_force_default_march = (machine == 'default')
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flags_common_default = [
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# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
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# to determine the best threshold in code. Refer to notes in source file
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# (lib/librte_eal/arm/include/rte_memcpy_64.h) for more info.
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['RTE_ARCH_ARM64_MEMCPY', false],
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# ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
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# ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
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# Leave below RTE_ARM64_MEMCPY_xxx options commented out, unless there're
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# strong reasons.
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# ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
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# ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
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# ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
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['RTE_LIBRTE_FM10K_PMD', false],
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['RTE_LIBRTE_SFC_EFX_PMD', false],
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['RTE_LIBRTE_AVP_PMD', false],
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['RTE_SCHED_VECTOR', false],
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['RTE_ARM_USE_WFE', false],
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]
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flags_generic = [
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['RTE_MACHINE', '"armv8a"'],
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['RTE_MAX_LCORE', 256],
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['RTE_USE_C11_MEM_MODEL', true],
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['RTE_CACHE_LINE_SIZE', 128]]
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flags_arm = [
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['RTE_MACHINE', '"armv8a"'],
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['RTE_MAX_LCORE', 16],
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['RTE_USE_C11_MEM_MODEL', true],
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['RTE_CACHE_LINE_SIZE', 64]]
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flags_cavium = [
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['RTE_CACHE_LINE_SIZE', 128],
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['RTE_MAX_NUMA_NODES', 2],
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['RTE_MAX_LCORE', 96],
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['RTE_MAX_VFIO_GROUPS', 128]]
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flags_dpaa = [
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['RTE_MACHINE', '"dpaa"'],
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['RTE_USE_C11_MEM_MODEL', true],
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['RTE_CACHE_LINE_SIZE', 64],
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['RTE_MAX_NUMA_NODES', 1],
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['RTE_MAX_LCORE', 16],
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['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
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flags_emag = [
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['RTE_MACHINE', '"emag"'],
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['RTE_CACHE_LINE_SIZE', 64],
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['RTE_MAX_NUMA_NODES', 1],
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['RTE_MAX_LCORE', 32]]
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flags_armada = [
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['RTE_MACHINE', '"armv8a"'],
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['RTE_CACHE_LINE_SIZE', 64],
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['RTE_MAX_NUMA_NODES', 1],
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['RTE_MAX_LCORE', 16]]
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flags_default_extra = []
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flags_n1sdp_extra = [
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['RTE_MACHINE', '"n1sdp"'],
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['RTE_MAX_NUMA_NODES', 1],
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['RTE_MAX_LCORE', 4],
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['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
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['RTE_LIBRTE_VHOST_NUMA', false]]
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flags_thunderx_extra = [
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['RTE_MACHINE', '"thunderx"'],
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['RTE_USE_C11_MEM_MODEL', false]]
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flags_thunderx2_extra = [
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['RTE_MACHINE', '"thunderx2"'],
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['RTE_CACHE_LINE_SIZE', 64],
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['RTE_MAX_NUMA_NODES', 2],
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['RTE_MAX_LCORE', 256],
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['RTE_ARM_FEATURE_ATOMICS', true],
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['RTE_USE_C11_MEM_MODEL', true]]
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flags_octeontx2_extra = [
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['RTE_MACHINE', '"octeontx2"'],
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['RTE_MAX_NUMA_NODES', 1],
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['RTE_MAX_LCORE', 36],
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['RTE_ARM_FEATURE_ATOMICS', true],
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['RTE_EAL_IGB_UIO', false],
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['RTE_USE_C11_MEM_MODEL', true]]
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machine_args_generic = [
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['default', ['-march=armv8-a+crc', '-moutline-atomics']],
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['native', ['-march=native']],
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['0xd03', ['-mcpu=cortex-a53']],
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['0xd04', ['-mcpu=cortex-a35']],
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['0xd07', ['-mcpu=cortex-a57']],
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['0xd08', ['-mcpu=cortex-a72']],
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['0xd09', ['-mcpu=cortex-a73']],
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['0xd0a', ['-mcpu=cortex-a75']],
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['0xd0b', ['-mcpu=cortex-a76']],
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['0xd0c', ['-march=armv8.2-a+crc+crypto', '-mcpu=neoverse-n1'], flags_n1sdp_extra]]
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machine_args_cavium = [
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['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
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['native', ['-march=native']],
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['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
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['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
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['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
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['0xaf', ['-march=armv8.1-a+crc+crypto','-mcpu=thunderx2t99'], flags_thunderx2_extra],
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['0xb2', ['-march=armv8.2-a+crc+crypto+lse','-mcpu=octeontx2'], flags_octeontx2_extra]]
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machine_args_emag = [
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['default', ['-march=armv8-a+crc+crypto', '-mtune=emag']],
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['native', ['-march=native']]]
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## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
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impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
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impl_0x41 = ['Arm', flags_arm, machine_args_generic]
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impl_0x42 = ['Broadcom', flags_generic, machine_args_generic]
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impl_0x43 = ['Cavium', flags_cavium, machine_args_cavium]
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impl_0x44 = ['DEC', flags_generic, machine_args_generic]
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impl_0x49 = ['Infineon', flags_generic, machine_args_generic]
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impl_0x4d = ['Motorola', flags_generic, machine_args_generic]
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impl_0x4e = ['NVIDIA', flags_generic, machine_args_generic]
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impl_0x50 = ['Ampere Computing', flags_emag, machine_args_emag]
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impl_0x51 = ['Qualcomm', flags_generic, machine_args_generic]
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impl_0x53 = ['Samsung', flags_generic, machine_args_generic]
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impl_0x56 = ['Marvell ARMADA', flags_armada, machine_args_generic]
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impl_0x69 = ['Intel', flags_generic, machine_args_generic]
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impl_dpaa = ['NXP DPAA', flags_dpaa, machine_args_generic]
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dpdk_conf.set('RTE_ARCH_ARM', 1)
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dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
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if dpdk_conf.get('RTE_ARCH_32')
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dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
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dpdk_conf.set('RTE_ARCH_ARMv7', 1)
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# the minimum architecture supported, armv7-a, needs the following,
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# mk/machine/armv7a/rte.vars.mk sets it too
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machine_args += '-mfpu=neon'
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else
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dpdk_conf.set('RTE_CACHE_LINE_SIZE', 128)
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dpdk_conf.set('RTE_ARCH_ARM64', 1)
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machine = []
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cmd_generic = ['generic', '', '', 'default', '']
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cmd_output = cmd_generic # Set generic by default
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machine_args = [] # Clear previous machine args
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if arm_force_default_march and not meson.is_cross_build()
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machine = impl_generic
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impl_pn = 'default'
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elif not meson.is_cross_build()
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# The script returns ['Implementer', 'Variant', 'Architecture',
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# 'Primary Part number', 'Revision']
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detect_vendor = find_program(join_paths(
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meson.current_source_dir(), 'armv8_machine.py'))
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cmd = run_command(detect_vendor.path())
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if cmd.returncode() == 0
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cmd_output = cmd.stdout().to_lower().strip().split(' ')
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endif
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# Set to generic if variable is not found
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machine = get_variable('impl_' + cmd_output[0], ['generic'])
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if machine[0] == 'generic'
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machine = impl_generic
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cmd_output = cmd_generic
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endif
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impl_pn = cmd_output[3]
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if arm_force_native_march == true
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impl_pn = 'native'
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endif
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else
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impl_id = meson.get_cross_property('implementor_id', 'generic')
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impl_pn = meson.get_cross_property('implementor_pn', 'default')
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machine = get_variable('impl_' + impl_id)
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endif
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# Apply Common Defaults. These settings may be overwritten by machine
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# settings later.
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foreach flag: flags_common_default
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if flag.length() > 0
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dpdk_conf.set(flag[0], flag[1])
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endif
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endforeach
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message('Implementer : ' + machine[0])
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foreach flag: machine[1]
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if flag.length() > 0
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dpdk_conf.set(flag[0], flag[1])
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endif
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endforeach
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foreach marg: machine[2]
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if marg[0] == impl_pn
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foreach flag: marg[1]
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if cc.has_argument(flag)
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machine_args += flag
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endif
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endforeach
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# Apply any extra machine specific flags.
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foreach flag: marg.get(2, flags_default_extra)
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if flag.length() > 0
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dpdk_conf.set(flag[0], flag[1])
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endif
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endforeach
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endif
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endforeach
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endif
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message(machine_args)
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if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
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cc.get_define('__aarch64__', args: machine_args) != '')
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compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
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endif
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if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
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compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
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endif
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if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
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compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
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'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']
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endif
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