3912fbde15
Add Traffic Management capability callbacks to provide global, level and node capabilities. This patch also adds documentation on Traffic Management Support. Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by: Krzysztof Kanas <kkanas@marvell.com> Acked-by: Jerin Jacob <jerinj@marvell.com>
171 lines
4.4 KiB
C
171 lines
4.4 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#ifndef __OTX2_TM_H__
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#define __OTX2_TM_H__
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#include <stdbool.h>
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#include <rte_tm_driver.h>
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#define NIX_TM_DEFAULT_TREE BIT_ULL(0)
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#define NIX_TM_COMMITTED BIT_ULL(1)
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#define NIX_TM_RATE_LIMIT_TREE BIT_ULL(2)
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#define NIX_TM_TL1_NO_SP BIT_ULL(3)
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struct otx2_eth_dev;
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void otx2_nix_tm_conf_init(struct rte_eth_dev *eth_dev);
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int otx2_nix_tm_init_default(struct rte_eth_dev *eth_dev);
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int otx2_nix_tm_fini(struct rte_eth_dev *eth_dev);
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int otx2_nix_tm_ops_get(struct rte_eth_dev *eth_dev, void *ops);
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int otx2_nix_tm_get_leaf_data(struct otx2_eth_dev *dev, uint16_t sq,
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uint32_t *rr_quantum, uint16_t *smq);
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int otx2_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev,
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uint16_t queue_idx, uint16_t tx_rate);
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int otx2_nix_sq_flush_pre(void *_txq, bool dev_started);
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int otx2_nix_sq_flush_post(void *_txq);
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int otx2_nix_sq_enable(void *_txq);
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int otx2_nix_get_link(struct otx2_eth_dev *dev);
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int otx2_nix_sq_sqb_aura_fc(void *_txq, bool enable);
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struct otx2_nix_tm_node {
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TAILQ_ENTRY(otx2_nix_tm_node) node;
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uint32_t id;
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uint32_t hw_id;
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uint32_t priority;
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uint32_t weight;
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uint16_t lvl;
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uint16_t hw_lvl;
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uint32_t rr_prio;
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uint32_t rr_num;
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uint32_t max_prio;
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uint32_t parent_hw_id;
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uint32_t flags:16;
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#define NIX_TM_NODE_HWRES BIT_ULL(0)
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#define NIX_TM_NODE_ENABLED BIT_ULL(1)
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#define NIX_TM_NODE_USER BIT_ULL(2)
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/* Shaper algorithm for RED state @NIX_REDALG_E */
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uint32_t red_algo:2;
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struct otx2_nix_tm_node *parent;
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struct rte_tm_node_params params;
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/* Last stats */
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uint64_t last_pkts;
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uint64_t last_bytes;
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};
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struct otx2_nix_tm_shaper_profile {
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TAILQ_ENTRY(otx2_nix_tm_shaper_profile) shaper;
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uint32_t shaper_profile_id;
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uint32_t reference_count;
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struct rte_tm_shaper_params params; /* Rate in bits/sec */
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};
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struct shaper_params {
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uint64_t burst_exponent;
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uint64_t burst_mantissa;
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uint64_t div_exp;
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uint64_t exponent;
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uint64_t mantissa;
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uint64_t burst;
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uint64_t rate;
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};
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TAILQ_HEAD(otx2_nix_tm_node_list, otx2_nix_tm_node);
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TAILQ_HEAD(otx2_nix_tm_shaper_profile_list, otx2_nix_tm_shaper_profile);
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#define MAX_SCHED_WEIGHT ((uint8_t)~0)
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#define NIX_TM_RR_QUANTUM_MAX (BIT_ULL(24) - 1)
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#define NIX_TM_WEIGHT_TO_RR_QUANTUM(__weight) \
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((((__weight) & MAX_SCHED_WEIGHT) * \
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NIX_TM_RR_QUANTUM_MAX) / MAX_SCHED_WEIGHT)
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/* DEFAULT_RR_WEIGHT * NIX_TM_RR_QUANTUM_MAX / MAX_SCHED_WEIGHT */
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/* = NIX_MAX_HW_MTU */
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#define DEFAULT_RR_WEIGHT 71
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/** NIX rate limits */
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#define MAX_RATE_DIV_EXP 12
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#define MAX_RATE_EXPONENT 0xf
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#define MAX_RATE_MANTISSA 0xff
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#define NIX_SHAPER_RATE_CONST ((uint64_t)2E6)
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/* NIX rate calculation in Bits/Sec
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* PIR_ADD = ((256 + NIX_*_PIR[RATE_MANTISSA])
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* << NIX_*_PIR[RATE_EXPONENT]) / 256
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* PIR = (2E6 * PIR_ADD / (1 << NIX_*_PIR[RATE_DIVIDER_EXPONENT]))
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*
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* CIR_ADD = ((256 + NIX_*_CIR[RATE_MANTISSA])
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* << NIX_*_CIR[RATE_EXPONENT]) / 256
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* CIR = (2E6 * CIR_ADD / (CCLK_TICKS << NIX_*_CIR[RATE_DIVIDER_EXPONENT]))
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*/
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#define SHAPER_RATE(exponent, mantissa, div_exp) \
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((NIX_SHAPER_RATE_CONST * ((256 + (mantissa)) << (exponent)))\
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/ (((1ull << (div_exp)) * 256)))
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/* 96xx rate limits in Bits/Sec */
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#define MIN_SHAPER_RATE \
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SHAPER_RATE(0, 0, MAX_RATE_DIV_EXP)
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#define MAX_SHAPER_RATE \
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SHAPER_RATE(MAX_RATE_EXPONENT, MAX_RATE_MANTISSA, 0)
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/** TM Shaper - low level operations */
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/** NIX burst limits */
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#define MAX_BURST_EXPONENT 0xf
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#define MAX_BURST_MANTISSA 0xff
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/* NIX burst calculation
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* PIR_BURST = ((256 + NIX_*_PIR[BURST_MANTISSA])
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* << (NIX_*_PIR[BURST_EXPONENT] + 1))
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* / 256
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*
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* CIR_BURST = ((256 + NIX_*_CIR[BURST_MANTISSA])
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* << (NIX_*_CIR[BURST_EXPONENT] + 1))
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* / 256
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*/
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#define SHAPER_BURST(exponent, mantissa) \
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(((256 + (mantissa)) << ((exponent) + 1)) / 256)
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/** Shaper burst limits */
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#define MIN_SHAPER_BURST \
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SHAPER_BURST(0, 0)
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#define MAX_SHAPER_BURST \
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SHAPER_BURST(MAX_BURST_EXPONENT,\
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MAX_BURST_MANTISSA)
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/* Default TL1 priority and Quantum from AF */
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#define TXSCH_TL1_DFLT_RR_QTM ((1 << 24) - 1)
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#define TXSCH_TL1_DFLT_RR_PRIO 1
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#define TXSCH_TLX_SP_PRIO_MAX 10
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static inline const char *
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nix_hwlvl2str(uint32_t hw_lvl)
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{
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switch (hw_lvl) {
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case NIX_TXSCH_LVL_MDQ:
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return "SMQ/MDQ";
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case NIX_TXSCH_LVL_TL4:
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return "TL4";
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case NIX_TXSCH_LVL_TL3:
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return "TL3";
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case NIX_TXSCH_LVL_TL2:
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return "TL2";
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case NIX_TXSCH_LVL_TL1:
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return "TL1";
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default:
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break;
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}
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return "???";
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}
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#endif /* __OTX2_TM_H__ */
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