edd0854815
A VF representor allocates queues from PF's pool of queues and use them for its Tx and Rx. It supports 1 Tx queue and 1 Rx queue. Implicit packet forwarding between representor queues and VF does not yet exist. It will be enabled in subsequent commits using flowman API. Signed-off-by: Hyong Youb Kim <hyonkim@cisco.com> Reviewed-by: John Daley <johndale@cisco.com>
478 lines
15 KiB
C
478 lines
15 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2008-2017 Cisco Systems, Inc. All rights reserved.
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* Copyright 2007 Nuova Systems, Inc. All rights reserved.
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*/
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#ifndef _ENIC_H_
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#define _ENIC_H_
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#include <rte_vxlan.h>
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#include <rte_ether.h>
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#include "vnic_enet.h"
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#include "vnic_dev.h"
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#include "vnic_flowman.h"
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#include "vnic_wq.h"
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#include "vnic_rq.h"
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#include "vnic_cq.h"
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#include "vnic_intr.h"
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#include "vnic_stats.h"
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#include "vnic_nic.h"
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#include "vnic_rss.h"
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#include "enic_res.h"
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#include "cq_enet_desc.h"
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#include <stdbool.h>
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#include <sys/queue.h>
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#include <rte_spinlock.h>
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#define DRV_NAME "enic_pmd"
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#define DRV_DESCRIPTION "Cisco VIC Ethernet NIC Poll-mode Driver"
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#define DRV_COPYRIGHT "Copyright 2008-2015 Cisco Systems, Inc"
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#define VLAN_ETH_HLEN 18
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#define ENICPMD_SETTING(enic, f) ((enic->config.flags & VENETF_##f) ? 1 : 0)
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#define ENICPMD_BDF_LENGTH 13 /* 0000:00:00.0'\0' */
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#define ENIC_CALC_IP_CKSUM 1
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#define ENIC_CALC_TCP_UDP_CKSUM 2
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#define ENIC_MAX_MTU 9000
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#define ENIC_PAGE_SIZE 4096
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#define PAGE_ROUND_UP(x) \
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((((unsigned long)(x)) + ENIC_PAGE_SIZE-1) & (~(ENIC_PAGE_SIZE-1)))
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#define ENICPMD_VFIO_PATH "/dev/vfio/vfio"
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/*#define ENIC_DESC_COUNT_MAKE_ODD (x) do{if ((~(x)) & 1) { (x)--; } }while(0)*/
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#define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */
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#define PCI_DEVICE_ID_CISCO_VIC_ENET_VF 0x0071 /* enet SRIOV VF */
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/* enet SRIOV Standalone vNic VF */
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#define PCI_DEVICE_ID_CISCO_VIC_ENET_SN 0x02B7
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/* Special Filter id for non-specific packet flagging. Don't change value */
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#define ENIC_MAGIC_FILTER_ID 0xffff
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#define ENICPMD_FDIR_MAX 64
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/*
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* Interrupt 0: LSC and errors
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* Interrupt 1: rx queue 0
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* Interrupt 2: rx queue 1
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* ...
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*/
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#define ENICPMD_LSC_INTR_OFFSET 0
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#define ENICPMD_RXQ_INTR_OFFSET 1
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struct enic_fdir_node {
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struct rte_eth_fdir_filter filter;
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uint16_t fltr_id;
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uint16_t rq_index;
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};
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struct enic_fdir {
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struct rte_eth_fdir_stats stats;
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struct rte_hash *hash;
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struct enic_fdir_node *nodes[ENICPMD_FDIR_MAX];
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uint32_t modes;
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uint32_t types_mask;
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void (*copy_fltr_fn)(struct filter_v2 *filt,
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const struct rte_eth_fdir_input *input,
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const struct rte_eth_fdir_masks *masks);
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};
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struct enic_soft_stats {
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rte_atomic64_t rx_nombuf;
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rte_atomic64_t rx_packet_errors;
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rte_atomic64_t tx_oversized;
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};
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struct enic_memzone_entry {
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const struct rte_memzone *rz;
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LIST_ENTRY(enic_memzone_entry) entries;
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};
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/* Defined in enic_fm_flow.c */
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struct enic_flowman;
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struct enic_fm_flow;
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struct rte_flow {
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LIST_ENTRY(rte_flow) next;
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/* Data for filter API based flow (enic_flow.c) */
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uint16_t enic_filter_id;
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struct filter_v2 enic_filter;
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/* Data for flow manager based flow (enic_fm_flow.c) */
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struct enic_fm_flow *fm;
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};
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/* Per-instance private data structure */
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struct enic {
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struct enic *next;
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struct rte_pci_device *pdev;
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struct vnic_enet_config config;
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struct vnic_dev_bar bar0;
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struct vnic_dev *vdev;
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/*
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* mbuf_initializer contains 64 bits of mbuf rearm_data, used by
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* the avx2 handler at this time.
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*/
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uint64_t mbuf_initializer;
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unsigned int port_id;
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bool overlay_offload;
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struct rte_eth_dev *rte_dev;
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struct rte_eth_dev_data *dev_data;
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struct enic_fdir fdir;
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char bdf_name[ENICPMD_BDF_LENGTH];
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int dev_fd;
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int iommu_group_fd;
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int iommu_groupid;
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int eventfd;
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uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
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pthread_t err_intr_thread;
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int promisc;
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int allmulti;
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uint8_t ig_vlan_strip_en;
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int link_status;
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uint8_t hw_ip_checksum;
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uint16_t max_mtu;
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uint8_t adv_filters;
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uint32_t flow_filter_mode;
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uint8_t filter_actions; /* HW supported actions */
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bool vxlan;
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bool disable_overlay; /* devargs disable_overlay=1 */
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uint8_t enable_avx2_rx; /* devargs enable-avx2-rx=1 */
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uint8_t geneve_opt_avail; /* Geneve with options offload available */
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uint8_t geneve_opt_enabled; /* Geneve with options offload enabled */
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uint8_t geneve_opt_request; /* devargs geneve-opt=1 */
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bool nic_cfg_chk; /* NIC_CFG_CHK available */
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bool udp_rss_weak; /* Bodega style UDP RSS */
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uint8_t ig_vlan_rewrite_mode; /* devargs ig-vlan-rewrite */
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uint16_t vxlan_port; /* current vxlan port pushed to NIC */
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int use_simple_tx_handler;
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int use_noscatter_vec_rx_handler;
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unsigned int flags;
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unsigned int priv_flags;
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/* work queue (len = conf_wq_count) */
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struct vnic_wq *wq;
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unsigned int wq_count; /* equals eth_dev nb_tx_queues */
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/* receive queue (len = conf_rq_count) */
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struct vnic_rq *rq;
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unsigned int rq_count; /* equals eth_dev nb_rx_queues */
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/* completion queue (len = conf_cq_count) */
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struct vnic_cq *cq;
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unsigned int cq_count; /* equals rq_count + wq_count */
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/* interrupt vectors (len = conf_intr_count) */
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struct vnic_intr *intr;
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unsigned int intr_count; /* equals enabled interrupts (lsc + rxqs) */
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/* software counters */
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struct enic_soft_stats soft_stats;
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/* configured resources on vic */
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unsigned int conf_rq_count;
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unsigned int conf_wq_count;
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unsigned int conf_cq_count;
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unsigned int conf_intr_count;
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/* linked list storing memory allocations */
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LIST_HEAD(enic_memzone_list, enic_memzone_entry) memzone_list;
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rte_spinlock_t memzone_list_lock;
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rte_spinlock_t mtu_lock;
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LIST_HEAD(enic_flows, rte_flow) flows;
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/* RSS */
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uint16_t reta_size;
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uint8_t hash_key_size;
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uint64_t flow_type_rss_offloads; /* 0 indicates RSS not supported */
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/*
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* Keep a copy of current RSS config for queries, as we cannot retrieve
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* it from the NIC.
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*/
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uint8_t rss_hash_type; /* NIC_CFG_RSS_HASH_TYPE flags */
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uint8_t rss_enable;
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uint64_t rss_hf; /* ETH_RSS flags */
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union vnic_rss_key rss_key;
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union vnic_rss_cpu rss_cpu;
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uint64_t rx_offload_capa; /* DEV_RX_OFFLOAD flags */
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uint64_t tx_offload_capa; /* DEV_TX_OFFLOAD flags */
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uint64_t tx_queue_offload_capa; /* DEV_TX_OFFLOAD flags */
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uint64_t tx_offload_mask; /* PKT_TX flags accepted */
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/* Multicast MAC addresses added to the NIC */
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uint32_t mc_count;
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struct rte_ether_addr mc_addrs[ENIC_MULTICAST_PERFECT_FILTERS];
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/* Flow manager API */
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struct enic_flowman *fm;
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/* switchdev */
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uint8_t switchdev_mode;
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uint16_t switch_domain_id;
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uint16_t max_vf_id;
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/* Number of queues needed for VF representor paths */
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uint32_t vf_required_wq;
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uint32_t vf_required_cq;
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uint32_t vf_required_rq;
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/*
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* Lock to serialize devcmds from PF, VF representors as they all share
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* the same PF devcmd instance in firmware.
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*/
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rte_spinlock_t devcmd_lock;
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};
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struct enic_vf_representor {
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struct enic enic;
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struct vnic_enet_config config;
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struct rte_eth_dev *eth_dev;
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struct rte_ether_addr mac_addr;
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struct rte_pci_addr bdf;
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struct enic *pf;
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uint16_t switch_domain_id;
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uint16_t vf_id;
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int allmulti;
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int promisc;
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/* Representor path uses PF queues. These are reserved during init */
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uint16_t pf_wq_idx; /* WQ dedicated to VF rep */
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uint16_t pf_wq_cq_idx; /* CQ for WQ */
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uint16_t pf_rq_sop_idx; /* SOP RQ dedicated to VF rep */
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uint16_t pf_rq_data_idx; /* Data RQ */
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};
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#define VF_ENIC_TO_VF_REP(vf_enic) \
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container_of(vf_enic, struct enic_vf_representor, enic)
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static inline int enic_is_vf_rep(struct enic *enic)
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{
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return !!(enic->rte_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR);
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}
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/* Compute ethdev's max packet size from MTU */
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static inline uint32_t enic_mtu_to_max_rx_pktlen(uint32_t mtu)
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{
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/* ethdev max size includes eth whereas NIC MTU does not */
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return mtu + RTE_ETHER_HDR_LEN;
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}
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/* Get the CQ index from a Start of Packet(SOP) RQ index */
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static inline unsigned int enic_sop_rq_idx_to_cq_idx(unsigned int sop_idx)
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{
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return sop_idx;
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}
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/* Get the RTE RQ index from a Start of Packet(SOP) RQ index */
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static inline unsigned int enic_sop_rq_idx_to_rte_idx(unsigned int sop_idx)
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{
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return sop_idx;
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}
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/* Get the Start of Packet(SOP) RQ index from a RTE RQ index */
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static inline unsigned int enic_rte_rq_idx_to_sop_idx(unsigned int rte_idx)
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{
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return rte_idx;
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}
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/* Get the Data RQ index from a RTE RQ index */
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static inline unsigned int enic_rte_rq_idx_to_data_idx(unsigned int rte_idx,
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struct enic *enic)
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{
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return enic->rq_count + rte_idx;
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}
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static inline unsigned int enic_vnic_rq_count(struct enic *enic)
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{
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return enic->rq_count * 2;
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}
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static inline unsigned int enic_cq_rq(__rte_unused struct enic *enic, unsigned int rq)
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{
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/* Scatter rx uses two receive queues together with one
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* completion queue, so the completion queue number is no
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* longer the same as the rq number.
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*/
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return rq;
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}
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static inline unsigned int enic_cq_wq(struct enic *enic, unsigned int wq)
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{
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return enic->rq_count + wq;
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}
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/*
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* WQ, RQ, CQ allocation scheme. Firmware gives the driver an array of
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* WQs, an array of RQs, and an array of CQs. Fow now, these are
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* statically allocated between PF app send/receive queues and VF
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* representor app send/receive queues. VF representor supports only 1
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* send and 1 receive queue. The number of PF app queue is not known
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* until the queue setup time.
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*
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* R = number of receive queues for PF app
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* S = number of send queues for PF app
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* V = number of VF representors
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*
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* wI = WQ for PF app send queue I
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* rI = SOP RQ for PF app receive queue I
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* dI = Data RQ for rI
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* cwI = CQ for wI
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* crI = CQ for rI
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* vwI = WQ for VF representor send queue I
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* vrI = SOP RQ for VF representor receive queue I
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* vdI = Data RQ for vrI
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* vcwI = CQ for vwI
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* vcrI = CQ for vrI
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*
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* WQ array: | w0 |..| wS-1 |..| vwV-1 |..| vw0 |
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* ^ ^ ^ ^
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* index 0 S-1 W-V W-1 W=len(WQ array)
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*
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* RQ array: | r0 |..| rR-1 |d0 |..|dR-1| ..|vdV-1 |..| vd0 |vrV-1 |..|vr0 |
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* ^ ^ ^ ^ ^ ^ ^ ^
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* index 0 R-1 R 2R-1 X-2V X-(V+1) X-V X-1
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* X=len(RQ array)
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*
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* CQ array: | cr0 |..| crR-1 |cw0|..|cwS-1|..|vcwV-1|..| vcw0|vcrV-1|..|vcr0|..
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* ^ ^ ^ ^ ^ ^ ^ ^
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* index 0 R-1 R R+S-1 X-2V X-(V+1) X-V X-1
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* X is not a typo. It really is len(RQ array) to accommodate enic_cq_rq() used
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* throughout RX handlers. The current scheme requires
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* len(CQ array) >= len(RQ array).
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*/
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static inline unsigned int vf_wq_cq_idx(struct enic_vf_representor *vf)
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{
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/* rq is not a typo. index(vcwI) coincides with index(vdI) */
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return vf->pf->conf_rq_count - (vf->pf->max_vf_id + vf->vf_id + 2);
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}
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static inline unsigned int vf_wq_idx(struct enic_vf_representor *vf)
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{
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return vf->pf->conf_wq_count - vf->vf_id - 1;
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}
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static inline unsigned int vf_rq_sop_idx(struct enic_vf_representor *vf)
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{
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return vf->pf->conf_rq_count - vf->vf_id - 1;
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}
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static inline unsigned int vf_rq_data_idx(struct enic_vf_representor *vf)
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{
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return vf->pf->conf_rq_count - (vf->pf->max_vf_id + vf->vf_id + 2);
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}
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static inline struct enic *pmd_priv(struct rte_eth_dev *eth_dev)
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{
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return eth_dev->data->dev_private;
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}
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static inline uint32_t
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enic_ring_add(uint32_t n_descriptors, uint32_t i0, uint32_t i1)
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{
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uint32_t d = i0 + i1;
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d -= (d >= n_descriptors) ? n_descriptors : 0;
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return d;
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}
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static inline uint32_t
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enic_ring_sub(uint32_t n_descriptors, uint32_t i0, uint32_t i1)
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{
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int32_t d = i1 - i0;
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return (uint32_t)((d < 0) ? ((int32_t)n_descriptors + d) : d);
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}
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static inline uint32_t
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enic_ring_incr(uint32_t n_descriptors, uint32_t idx)
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{
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idx++;
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if (unlikely(idx == n_descriptors))
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idx = 0;
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return idx;
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}
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int dev_is_enic(struct rte_eth_dev *dev);
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void enic_fdir_stats_get(struct enic *enic,
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struct rte_eth_fdir_stats *stats);
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int enic_fdir_add_fltr(struct enic *enic,
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struct rte_eth_fdir_filter *params);
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int enic_fdir_del_fltr(struct enic *enic,
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struct rte_eth_fdir_filter *params);
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void enic_free_wq(void *txq);
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int enic_alloc_intr_resources(struct enic *enic);
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int enic_setup_finish(struct enic *enic);
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int enic_alloc_wq(struct enic *enic, uint16_t queue_idx,
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unsigned int socket_id, uint16_t nb_desc);
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void enic_start_wq(struct enic *enic, uint16_t queue_idx);
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int enic_stop_wq(struct enic *enic, uint16_t queue_idx);
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void enic_start_rq(struct enic *enic, uint16_t queue_idx);
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int enic_stop_rq(struct enic *enic, uint16_t queue_idx);
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void enic_free_rq(void *rxq);
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int enic_alloc_rq(struct enic *enic, uint16_t queue_idx,
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unsigned int socket_id, struct rte_mempool *mp,
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uint16_t nb_desc, uint16_t free_thresh);
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int enic_set_vnic_res(struct enic *enic);
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int enic_init_rss_nic_cfg(struct enic *enic);
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int enic_set_rss_conf(struct enic *enic,
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struct rte_eth_rss_conf *rss_conf);
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int enic_set_rss_reta(struct enic *enic, union vnic_rss_cpu *rss_cpu);
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int enic_set_vlan_strip(struct enic *enic);
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int enic_enable(struct enic *enic);
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int enic_disable(struct enic *enic);
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void enic_remove(struct enic *enic);
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int enic_get_link_status(struct enic *enic);
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int enic_dev_stats_get(struct enic *enic,
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struct rte_eth_stats *r_stats);
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int enic_dev_stats_clear(struct enic *enic);
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int enic_add_packet_filter(struct enic *enic);
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int enic_set_mac_address(struct enic *enic, uint8_t *mac_addr);
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int enic_del_mac_address(struct enic *enic, int mac_index);
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unsigned int enic_cleanup_wq(struct enic *enic, struct vnic_wq *wq);
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void enic_send_pkt(struct enic *enic, struct vnic_wq *wq,
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struct rte_mbuf *tx_pkt, unsigned short len,
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uint8_t sop, uint8_t eop, uint8_t cq_entry,
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uint16_t ol_flags, uint16_t vlan_tag);
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void enic_post_wq_index(struct vnic_wq *wq);
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int enic_probe(struct enic *enic);
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int enic_clsf_init(struct enic *enic);
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void enic_clsf_destroy(struct enic *enic);
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int enic_fm_init(struct enic *enic);
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void enic_fm_destroy(struct enic *enic);
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void *enic_alloc_consistent(void *priv, size_t size, dma_addr_t *dma_handle,
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uint8_t *name);
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void enic_free_consistent(void *priv, size_t size, void *vaddr,
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dma_addr_t dma_handle);
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uint16_t enic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t enic_noscatter_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t enic_dummy_recv_pkts(void *rx_queue,
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struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t enic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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uint16_t enic_simple_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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uint16_t enic_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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int enic_set_mtu(struct enic *enic, uint16_t new_mtu);
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int enic_link_update(struct rte_eth_dev *eth_dev);
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bool enic_use_vector_rx_handler(struct rte_eth_dev *eth_dev);
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void enic_pick_rx_handler(struct rte_eth_dev *eth_dev);
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void enic_pick_tx_handler(struct rte_eth_dev *eth_dev);
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void enic_fdir_info(struct enic *enic);
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void enic_fdir_info_get(struct enic *enic, struct rte_eth_fdir_info *stats);
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int enic_vf_representor_init(struct rte_eth_dev *eth_dev, void *init_params);
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int enic_vf_representor_uninit(struct rte_eth_dev *ethdev);
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int enic_fm_allocate_switch_domain(struct enic *pf);
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int enic_alloc_rx_queue_mbufs(struct enic *enic, struct vnic_rq *rq);
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void enic_rxmbuf_queue_release(struct enic *enic, struct vnic_rq *rq);
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void enic_free_wq_buf(struct rte_mbuf **buf);
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void enic_free_rq_buf(struct rte_mbuf **mbuf);
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extern const struct rte_flow_ops enic_flow_ops;
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extern const struct rte_flow_ops enic_fm_flow_ops;
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#endif /* _ENIC_H_ */
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