numam-dpdk/doc
Viacheslav Ovsiienko f078ceb6ae net/mlx5: fix Tx doorbell write memory barrier
As the result of testing it was found that some hosts have
the performance penalty imposed by required write memory barrier
after doorbell writing. Before 19.08 release there was some
heuristics to decide whether write memory barrier should be
performed. For the bursts of recommended size (or multiple)
it was supposed there were some extra ongoing packets in the
next burst and write memory barrier may be skipped (supposed
to be performed in the next burst, at least after descriptor
writing).

This patch restores that behaviour, the devargs tx_db_nc=2
must be specified to engage this performance tuning feature.

Fixes: 8409a28573 ("net/mlx5: control transmit doorbell register mapping")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-11-20 17:36:06 +01:00
..
api doc: add ice PMD in doxygen 2019-11-11 14:23:02 +01:00
guides net/mlx5: fix Tx doorbell write memory barrier 2019-11-20 17:36:06 +01:00
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