8efa348e81
Adding cnxk device driver support to configure custom SA index. Custom SA index can be configured as part of the session create as SPI, and later original SPI can be updated using session update. Signed-off-by: Kiran Kumar K <kirankumark@marvell.com> Acked-by: Ray Kinsella <mdr@ashroe.eu> Acked-by: Jerin Jacob <jerinj@marvell.com>
197 lines
5.7 KiB
Meson
197 lines
5.7 KiB
Meson
# SPDX-License-Identifier: BSD-3-Clause
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# Copyright(C) 2021 Marvell.
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#
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if not dpdk_conf.get('RTE_ARCH_64')
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build = false
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reason = 'only supported on 64-bit'
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subdir_done()
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endif
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sources = files(
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'cnxk_ethdev.c',
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'cnxk_ethdev_devargs.c',
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'cnxk_ethdev_mtr.c',
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'cnxk_ethdev_ops.c',
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'cnxk_ethdev_sec.c',
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'cnxk_ethdev_telemetry.c',
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'cnxk_ethdev_sec_telemetry.c',
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'cnxk_link.c',
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'cnxk_lookup.c',
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'cnxk_ptp.c',
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'cnxk_flow.c',
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'cnxk_stats.c',
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'cnxk_tm.c',
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)
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# CN9K
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sources += files(
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'cn9k_ethdev.c',
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'cn9k_ethdev_sec.c',
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'cn9k_flow.c',
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'cn9k_rx_select.c',
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'cn9k_tx_select.c',
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)
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sources += files(
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'rx/cn9k/rx_0_15.c',
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'rx/cn9k/rx_16_31.c',
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'rx/cn9k/rx_32_47.c',
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'rx/cn9k/rx_48_63.c',
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'rx/cn9k/rx_64_79.c',
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'rx/cn9k/rx_80_95.c',
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'rx/cn9k/rx_96_111.c',
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'rx/cn9k/rx_112_127.c',
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'rx/cn9k/rx_0_15_mseg.c',
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'rx/cn9k/rx_16_31_mseg.c',
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'rx/cn9k/rx_32_47_mseg.c',
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'rx/cn9k/rx_48_63_mseg.c',
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'rx/cn9k/rx_64_79_mseg.c',
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'rx/cn9k/rx_80_95_mseg.c',
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'rx/cn9k/rx_96_111_mseg.c',
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'rx/cn9k/rx_112_127_mseg.c',
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'rx/cn9k/rx_0_15_vec.c',
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'rx/cn9k/rx_16_31_vec.c',
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'rx/cn9k/rx_32_47_vec.c',
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'rx/cn9k/rx_48_63_vec.c',
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'rx/cn9k/rx_64_79_vec.c',
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'rx/cn9k/rx_80_95_vec.c',
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'rx/cn9k/rx_96_111_vec.c',
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'rx/cn9k/rx_112_127_vec.c',
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'rx/cn9k/rx_0_15_vec_mseg.c',
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'rx/cn9k/rx_16_31_vec_mseg.c',
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'rx/cn9k/rx_32_47_vec_mseg.c',
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'rx/cn9k/rx_48_63_vec_mseg.c',
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'rx/cn9k/rx_64_79_vec_mseg.c',
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'rx/cn9k/rx_80_95_vec_mseg.c',
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'rx/cn9k/rx_96_111_vec_mseg.c',
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'rx/cn9k/rx_112_127_vec_mseg.c',
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)
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sources += files(
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'tx/cn9k/tx_0_15.c',
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'tx/cn9k/tx_16_31.c',
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'tx/cn9k/tx_32_47.c',
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'tx/cn9k/tx_48_63.c',
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'tx/cn9k/tx_64_79.c',
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'tx/cn9k/tx_80_95.c',
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'tx/cn9k/tx_96_111.c',
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'tx/cn9k/tx_112_127.c',
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'tx/cn9k/tx_0_15_mseg.c',
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'tx/cn9k/tx_16_31_mseg.c',
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'tx/cn9k/tx_32_47_mseg.c',
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'tx/cn9k/tx_48_63_mseg.c',
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'tx/cn9k/tx_64_79_mseg.c',
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'tx/cn9k/tx_80_95_mseg.c',
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'tx/cn9k/tx_96_111_mseg.c',
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'tx/cn9k/tx_112_127_mseg.c',
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'tx/cn9k/tx_0_15_vec.c',
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'tx/cn9k/tx_16_31_vec.c',
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'tx/cn9k/tx_32_47_vec.c',
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'tx/cn9k/tx_48_63_vec.c',
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'tx/cn9k/tx_64_79_vec.c',
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'tx/cn9k/tx_80_95_vec.c',
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'tx/cn9k/tx_96_111_vec.c',
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'tx/cn9k/tx_112_127_vec.c',
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'tx/cn9k/tx_0_15_vec_mseg.c',
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'tx/cn9k/tx_16_31_vec_mseg.c',
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'tx/cn9k/tx_32_47_vec_mseg.c',
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'tx/cn9k/tx_48_63_vec_mseg.c',
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'tx/cn9k/tx_64_79_vec_mseg.c',
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'tx/cn9k/tx_80_95_vec_mseg.c',
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'tx/cn9k/tx_96_111_vec_mseg.c',
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'tx/cn9k/tx_112_127_vec_mseg.c',
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)
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# CN10K
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sources += files(
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'cn10k_ethdev.c',
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'cn10k_ethdev_sec.c',
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'cn10k_flow.c',
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'cn10k_rx_select.c',
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'cn10k_tx_select.c',
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)
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sources += files(
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'rx/cn10k/rx_0_15.c',
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'rx/cn10k/rx_16_31.c',
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'rx/cn10k/rx_32_47.c',
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'rx/cn10k/rx_48_63.c',
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'rx/cn10k/rx_64_79.c',
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'rx/cn10k/rx_80_95.c',
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'rx/cn10k/rx_96_111.c',
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'rx/cn10k/rx_112_127.c',
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'rx/cn10k/rx_0_15_mseg.c',
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'rx/cn10k/rx_16_31_mseg.c',
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'rx/cn10k/rx_32_47_mseg.c',
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'rx/cn10k/rx_48_63_mseg.c',
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'rx/cn10k/rx_64_79_mseg.c',
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'rx/cn10k/rx_80_95_mseg.c',
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'rx/cn10k/rx_96_111_mseg.c',
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'rx/cn10k/rx_112_127_mseg.c',
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'rx/cn10k/rx_0_15_vec.c',
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'rx/cn10k/rx_16_31_vec.c',
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'rx/cn10k/rx_32_47_vec.c',
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'rx/cn10k/rx_48_63_vec.c',
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'rx/cn10k/rx_64_79_vec.c',
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'rx/cn10k/rx_80_95_vec.c',
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'rx/cn10k/rx_96_111_vec.c',
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'rx/cn10k/rx_112_127_vec.c',
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'rx/cn10k/rx_0_15_vec_mseg.c',
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'rx/cn10k/rx_16_31_vec_mseg.c',
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'rx/cn10k/rx_32_47_vec_mseg.c',
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'rx/cn10k/rx_48_63_vec_mseg.c',
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'rx/cn10k/rx_64_79_vec_mseg.c',
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'rx/cn10k/rx_80_95_vec_mseg.c',
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'rx/cn10k/rx_96_111_vec_mseg.c',
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'rx/cn10k/rx_112_127_vec_mseg.c',
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)
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sources += files(
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'tx/cn10k/tx_0_15.c',
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'tx/cn10k/tx_16_31.c',
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'tx/cn10k/tx_32_47.c',
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'tx/cn10k/tx_48_63.c',
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'tx/cn10k/tx_64_79.c',
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'tx/cn10k/tx_80_95.c',
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'tx/cn10k/tx_96_111.c',
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'tx/cn10k/tx_112_127.c',
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'tx/cn10k/tx_0_15_mseg.c',
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'tx/cn10k/tx_16_31_mseg.c',
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'tx/cn10k/tx_32_47_mseg.c',
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'tx/cn10k/tx_48_63_mseg.c',
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'tx/cn10k/tx_64_79_mseg.c',
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'tx/cn10k/tx_80_95_mseg.c',
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'tx/cn10k/tx_96_111_mseg.c',
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'tx/cn10k/tx_112_127_mseg.c',
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'tx/cn10k/tx_0_15_vec.c',
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'tx/cn10k/tx_16_31_vec.c',
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'tx/cn10k/tx_32_47_vec.c',
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'tx/cn10k/tx_48_63_vec.c',
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'tx/cn10k/tx_64_79_vec.c',
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'tx/cn10k/tx_80_95_vec.c',
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'tx/cn10k/tx_96_111_vec.c',
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'tx/cn10k/tx_112_127_vec.c',
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'tx/cn10k/tx_0_15_vec_mseg.c',
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'tx/cn10k/tx_16_31_vec_mseg.c',
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'tx/cn10k/tx_32_47_vec_mseg.c',
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'tx/cn10k/tx_48_63_vec_mseg.c',
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'tx/cn10k/tx_64_79_vec_mseg.c',
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'tx/cn10k/tx_80_95_vec_mseg.c',
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'tx/cn10k/tx_96_111_vec_mseg.c',
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'tx/cn10k/tx_112_127_vec_mseg.c',
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)
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deps += ['bus_pci', 'cryptodev', 'eventdev', 'security']
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deps += ['common_cnxk', 'mempool_cnxk']
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# Allow implicit vector conversions and strict aliasing warning
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extra_flags = ['-flax-vector-conversions', '-Wno-strict-aliasing']
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foreach flag: extra_flags
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if cc.has_argument(flag)
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cflags += flag
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endif
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endforeach
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headers = files('rte_pmd_cnxk.h')
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