c752998b5e
The PCI lib defines the types and methods allowing to use PCI elements. The PCI bus implements a bus driver for PCI devices by constructing rte_bus elements using the PCI lib. Move the relevant code out of the EAL to its expected place. Libraries, drivers, unit tests and applications are updated to use the new rte_bus_pci.h header when necessary. Signed-off-by: Gaetan Rivet <gaetan.rivet@6wind.com>
104 lines
2.1 KiB
C
104 lines
2.1 KiB
C
#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <unistd.h>
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#include <errno.h>
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#include <sys/file.h>
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#include <sys/stat.h>
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#include <fcntl.h>
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#include <sys/types.h>
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#include <rte_bus_pci.h>
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#include <rte_malloc.h>
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#include "nfp_nfpu.h"
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/* PF BAR and expansion BAR for the NSP interface */
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#define NFP_CFG_PCIE_BAR 0
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#define NFP_CFG_EXP_BAR 7
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#define NFP_CFG_EXP_BAR_CFG_BASE 0x30000
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/* There could be other NFP userspace tools using the NSP interface.
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* Make sure there is no other process using it and locking the access for
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* avoiding problems.
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*/
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static int
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nspv_aquire_process_lock(nfpu_desc_t *desc)
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{
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int rc;
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struct flock lock;
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char lockname[30];
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memset(&lock, 0, sizeof(lock));
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snprintf(lockname, sizeof(lockname), "/var/lock/nfp%d", desc->nfp);
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/* Using S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH */
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desc->lock = open(lockname, O_RDWR | O_CREAT, 0666);
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if (desc->lock < 0)
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return desc->lock;
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lock.l_type = F_WRLCK;
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lock.l_whence = SEEK_SET;
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rc = -1;
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while (rc != 0) {
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rc = fcntl(desc->lock, F_SETLK, &lock);
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if (rc < 0) {
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if ((errno != EAGAIN) && (errno != EACCES)) {
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close(desc->lock);
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return rc;
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}
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}
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}
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return 0;
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}
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int
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nfpu_open(struct rte_pci_device *pci_dev, nfpu_desc_t *desc, int nfp)
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{
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void *cfg_base, *mem_base;
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size_t barsz;
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int ret = 0;
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int i = 0;
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desc->nfp = nfp;
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ret = nspv_aquire_process_lock(desc);
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if (ret)
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return -1;
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barsz = pci_dev->mem_resource[0].len;
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/* barsz in log2 */
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while (barsz >>= 1)
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i++;
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barsz = i;
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/* Getting address for NFP expansion BAR registers */
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cfg_base = pci_dev->mem_resource[0].addr;
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cfg_base = (uint8_t *)cfg_base + NFP_CFG_EXP_BAR_CFG_BASE;
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/* Getting address for NFP NSP interface registers */
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mem_base = pci_dev->mem_resource[0].addr;
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mem_base = (uint8_t *)mem_base + (NFP_CFG_EXP_BAR << (barsz - 3));
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desc->nspu = rte_malloc("nfp nspu", sizeof(nspu_desc_t), 0);
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nfp_nspu_init(desc->nspu, desc->nfp, NFP_CFG_PCIE_BAR, barsz,
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NFP_CFG_EXP_BAR, cfg_base, mem_base);
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return ret;
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}
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int
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nfpu_close(nfpu_desc_t *desc)
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{
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rte_free(desc->nspu);
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close(desc->lock);
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unlink("/var/lock/nfp0");
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return 0;
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}
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