1ee9569576
This patch enables the NXP DPAA & DPAA2 drivers for ARMV8 targets. They can be used with standard armv8 config with command line mempool argument or newly introduced platform mempool internal registration mechanism. Note that the dpaa(x) specific config files are still preserved to continue customer support. They also contain some of the ARM performance tuning flags. e.g the default ARM cache size of 128 is not optimal for NXP platforms. However, these configs will eventually be removed once a dynamic mechanisms are developed to detect the performance settings. Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
31 lines
760 B
Plaintext
31 lines
760 B
Plaintext
# SPDX-License-Identifier: BSD-3-Clause
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# Copyright 2016 Freescale Semiconductor, Inc.
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# Copyright 2017 NXP
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#include "defconfig_arm64-armv8a-linuxapp-gcc"
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# NXP (Freescale) - Soc Architecture with FMAN, QMAN & BMAN support
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CONFIG_RTE_MACHINE="dpaa"
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CONFIG_RTE_ARCH_ARM_TUNE="cortex-a72"
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CONFIG_RTE_LIBRTE_VHOST_NUMA=n
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CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
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#
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# Compile Environment Abstraction Layer
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#
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CONFIG_RTE_MAX_LCORE=4
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CONFIG_RTE_MAX_NUMA_NODES=1
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CONFIG_RTE_CACHE_LINE_SIZE=64
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CONFIG_RTE_PKTMBUF_HEADROOM=128
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# NXP DPAA Bus
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CONFIG_RTE_LIBRTE_DPAA_DEBUG_DRIVER=n
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CONFIG_RTE_LIBRTE_DPAA_HWDEBUG=n
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#
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# FSL DPAA caam - crypto driver
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#
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CONFIG_RTE_LIBRTE_DPAA_SEC_DEBUG_INIT=n
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CONFIG_RTE_LIBRTE_DPAA_SEC_DEBUG_DRIVER=n
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CONFIG_RTE_LIBRTE_DPAA_SEC_DEBUG_RX=n
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