UMR (User-Mode Memory Registration) WQE can present data buffers scattered within multiple mbufs with single indirect mkey. Take advantage of the UMR WQE, scattered mbuf in one operation can be presented to an indirect mkey. The RegEx which only accepts one mkey can now process the whole scattered mbuf in one operation. The maximum scattered mbuf can be supported in one UMR WQE is now defined as 64. The mbufs from multiple operations can be combined into one UMR WQE as well if there is enough space in the KLM array, since the operations can address their own mbuf's content by the mkey's address and length. However, one operation's scattered mbuf's can't be placed in two different UMR WQE's KLM array, if the UMR WQE's KLM does not has enough free space for one operation, the extra UMR WQE will be engaged. In case the UMR WQE's indirect mkey will be over wrapped by the SQ's WQE move, the mkey's index used by the UMR WQE should be the index of last the RegEX WQE in the operations. As one operation consumes one WQE set, build the RegEx WQE by reverse helps address the mkey more efficiently. Once the operations in one burst consumes multiple mkeys, when the mkey KLM array is full, the reverse WQE set index will always be the last of the new mkey's for the new UMR WQE. In GGA mode, the SQ WQE's memory layout becomes UMR/NOP and RegEx WQE by interleave. The UMR and RegEx WQE can be called as WQE set. The SQ's pi and ci will also be increased as WQE set not as WQE. For operations don't have scattered mbuf, uses the mbuf's mkey directly, the WQE set combination is NOP + RegEx. For operations have scattered mbuf but share the UMR WQE with others, the WQE set combination is NOP + RegEx. For operations complete the UMR WQE, the WQE set combination is UMR + RegEx. Signed-off-by: John Hurley <jhurley@nvidia.com> Signed-off-by: Suanming Mou <suanmingm@nvidia.com> Acked-by: Ori Kam <orika@nvidia.com>
273 lines
6.1 KiB
C
273 lines
6.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2020 Mellanox Technologies, Ltd
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*/
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#include <errno.h>
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#include <rte_log.h>
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#include <rte_errno.h>
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#include <rte_memory.h>
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#include <rte_malloc.h>
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#include <rte_regexdev.h>
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#include <rte_regexdev_core.h>
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#include <rte_regexdev_driver.h>
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#include <rte_dev.h>
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#include <mlx5_common.h>
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#include <mlx5_glue.h>
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#include <mlx5_devx_cmds.h>
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#include <mlx5_prm.h>
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#include <mlx5_common_os.h>
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#include <mlx5_common_devx.h>
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#include "mlx5_regex.h"
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#include "mlx5_regex_utils.h"
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#include "mlx5_rxp_csrs.h"
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#include "mlx5_rxp.h"
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#define MLX5_REGEX_NUM_WQE_PER_PAGE (4096/64)
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#define MLX5_REGEX_WQE_LOG_NUM(has_umr, log_desc) \
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((has_umr) ? ((log_desc) + 2) : (log_desc))
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/**
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* Returns the number of qp obj to be created.
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*
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* @param nb_desc
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* The number of descriptors for the queue.
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*
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* @return
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* The number of obj to be created.
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*/
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static uint16_t
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regex_ctrl_get_nb_obj(uint16_t nb_desc)
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{
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return ((nb_desc / MLX5_REGEX_NUM_WQE_PER_PAGE) +
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!!(nb_desc % MLX5_REGEX_NUM_WQE_PER_PAGE));
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}
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/**
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* destroy CQ.
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*
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* @param cp
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* Pointer to the CQ to be destroyed.
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*
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* @return
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* 0 on success, a negative errno value otherwise and rte_errno is set.
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*/
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static int
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regex_ctrl_destroy_cq(struct mlx5_regex_cq *cq)
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{
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mlx5_devx_cq_destroy(&cq->cq_obj);
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memset(cq, 0, sizeof(*cq));
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return 0;
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}
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/**
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* create the CQ object.
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*
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* @param priv
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* Pointer to the priv object.
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* @param cp
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* Pointer to the CQ to be created.
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*
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* @return
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* 0 on success, a negative errno value otherwise and rte_errno is set.
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*/
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static int
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regex_ctrl_create_cq(struct mlx5_regex_priv *priv, struct mlx5_regex_cq *cq)
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{
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struct mlx5_devx_cq_attr attr = {
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.uar_page_id = priv->uar->page_id,
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};
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int ret;
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cq->ci = 0;
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ret = mlx5_devx_cq_create(priv->ctx, &cq->cq_obj, cq->log_nb_desc,
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&attr, SOCKET_ID_ANY);
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if (ret) {
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DRV_LOG(ERR, "Can't create CQ object.");
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memset(cq, 0, sizeof(*cq));
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rte_errno = ENOMEM;
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return -rte_errno;
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}
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return 0;
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}
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/**
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* Destroy the SQ object.
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*
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* @param qp
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* Pointer to the QP element
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* @param q_ind
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* The index of the queue.
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*
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* @return
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* 0 on success, a negative errno value otherwise and rte_errno is set.
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*/
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static int
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regex_ctrl_destroy_sq(struct mlx5_regex_qp *qp, uint16_t q_ind)
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{
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struct mlx5_regex_sq *sq = &qp->sqs[q_ind];
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mlx5_devx_sq_destroy(&sq->sq_obj);
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memset(sq, 0, sizeof(*sq));
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return 0;
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}
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/**
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* create the SQ object.
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*
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* @param priv
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* Pointer to the priv object.
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* @param qp
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* Pointer to the QP element
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* @param q_ind
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* The index of the queue.
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* @param log_nb_desc
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* Log 2 of the number of descriptors to be used.
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*
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* @return
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* 0 on success, a negative errno value otherwise and rte_errno is set.
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*/
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static int
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regex_ctrl_create_sq(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,
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uint16_t q_ind, uint16_t log_nb_desc)
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{
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#ifdef HAVE_IBV_FLOW_DV_SUPPORT
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struct mlx5_devx_create_sq_attr attr = {
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.user_index = q_ind,
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.cqn = qp->cq.cq_obj.cq->id,
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.wq_attr = (struct mlx5_devx_wq_attr){
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.uar_page = priv->uar->page_id,
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},
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.ts_format = mlx5_ts_format_conv(priv->sq_ts_format),
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};
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struct mlx5_devx_modify_sq_attr modify_attr = {
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.state = MLX5_SQC_STATE_RDY,
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};
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struct mlx5_regex_sq *sq = &qp->sqs[q_ind];
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uint32_t pd_num = 0;
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int ret;
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sq->log_nb_desc = log_nb_desc;
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sq->sqn = q_ind;
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sq->ci = 0;
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sq->pi = 0;
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ret = regex_get_pdn(priv->pd, &pd_num);
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if (ret)
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return ret;
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attr.wq_attr.pd = pd_num;
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ret = mlx5_devx_sq_create(priv->ctx, &sq->sq_obj,
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MLX5_REGEX_WQE_LOG_NUM(priv->has_umr, log_nb_desc),
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&attr, SOCKET_ID_ANY);
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if (ret) {
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DRV_LOG(ERR, "Can't create SQ object.");
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rte_errno = ENOMEM;
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return -rte_errno;
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}
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ret = mlx5_devx_cmd_modify_sq(sq->sq_obj.sq, &modify_attr);
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if (ret) {
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DRV_LOG(ERR, "Can't change SQ state to ready.");
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regex_ctrl_destroy_sq(qp, q_ind);
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rte_errno = ENOMEM;
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return -rte_errno;
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}
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return 0;
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#else
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(void)priv;
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(void)qp;
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(void)q_ind;
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(void)log_nb_desc;
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DRV_LOG(ERR, "Cannot get pdn - no DV support.");
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return -ENOTSUP;
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#endif
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}
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/**
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* Setup the qp.
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*
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* @param dev
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* Pointer to RegEx dev structure.
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* @param qp_ind
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* The queue index to setup.
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* @param cfg
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* The queue requested configuration.
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*
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* @return
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* 0 on success, a negative errno value otherwise and rte_errno is set.
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*/
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int
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mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind,
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const struct rte_regexdev_qp_conf *cfg)
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{
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struct mlx5_regex_priv *priv = dev->data->dev_private;
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struct mlx5_regex_qp *qp;
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int i;
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int nb_sq_config = 0;
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int ret;
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uint16_t log_desc;
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qp = &priv->qps[qp_ind];
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qp->flags = cfg->qp_conf_flags;
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log_desc = rte_log2_u32(cfg->nb_desc);
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/*
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* UMR mode requires two WQEs(UMR and RegEx WQE) for one descriptor.
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* For CQ, expand the CQE number multiple with 2.
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* For SQ, the UMR and RegEx WQE for one descriptor consumes 4 WQEBBS,
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* expand the WQE number multiple with 4.
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*/
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qp->cq.log_nb_desc = log_desc + (!!priv->has_umr);
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qp->nb_desc = 1 << log_desc;
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if (qp->flags & RTE_REGEX_QUEUE_PAIR_CFG_OOS_F)
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qp->nb_obj = regex_ctrl_get_nb_obj
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(1 << MLX5_REGEX_WQE_LOG_NUM(priv->has_umr, log_desc));
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else
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qp->nb_obj = 1;
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qp->sqs = rte_malloc(NULL,
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qp->nb_obj * sizeof(struct mlx5_regex_sq), 64);
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if (!qp->sqs) {
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DRV_LOG(ERR, "Can't allocate sq array memory.");
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rte_errno = ENOMEM;
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return -rte_errno;
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}
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log_desc = rte_log2_u32(qp->nb_desc / qp->nb_obj);
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ret = regex_ctrl_create_cq(priv, &qp->cq);
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if (ret) {
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DRV_LOG(ERR, "Can't create cq.");
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goto err_cq;
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}
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for (i = 0; i < qp->nb_obj; i++) {
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ret = regex_ctrl_create_sq(priv, qp, i, log_desc);
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if (ret) {
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DRV_LOG(ERR, "Can't create sq.");
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goto err_btree;
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}
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nb_sq_config++;
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}
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ret = mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N,
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rte_socket_id());
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if (ret) {
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DRV_LOG(ERR, "Error setting up mr btree");
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goto err_btree;
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}
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ret = mlx5_regexdev_setup_fastpath(priv, qp_ind);
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if (ret) {
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DRV_LOG(ERR, "Error setting up fastpath");
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goto err_fp;
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}
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return 0;
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err_fp:
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mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);
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err_btree:
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for (i = 0; i < nb_sq_config; i++)
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regex_ctrl_destroy_sq(qp, i);
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regex_ctrl_destroy_cq(&qp->cq);
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err_cq:
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rte_free(qp->sqs);
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return ret;
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}
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