4382a7ccf7
Add support to receive CPT processed packets on Rx via second pass on CN10K. Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Acked-by: Jerin Jacob <jerinj@marvell.com>
89 lines
2.8 KiB
C
89 lines
2.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 Marvell.
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*/
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#include "cn10k_ethdev.h"
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#include "cn10k_rx.h"
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#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
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uint16_t __rte_noinline __rte_hot cn10k_nix_recv_pkts_##name( \
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void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \
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{ \
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return cn10k_nix_recv_pkts(rx_queue, rx_pkts, pkts, (flags)); \
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} \
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NIX_RX_FASTPATH_MODES
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#undef R
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static inline void
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pick_rx_func(struct rte_eth_dev *eth_dev,
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const eth_rx_burst_t rx_burst[2][2][2][2][2][2][2])
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{
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struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
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/* [VLAN] [TSP] [MARK] [CKSUM] [PTYPE] [RSS] */
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eth_dev->rx_pkt_burst = rx_burst
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[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_SECURITY_F)]
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[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
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[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_TSTAMP_F)]
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[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
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[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_CHECKSUM_F)]
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[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_PTYPE_F)]
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[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_RSS_F)];
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rte_atomic_thread_fence(__ATOMIC_RELEASE);
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}
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void
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cn10k_eth_set_rx_function(struct rte_eth_dev *eth_dev)
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{
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struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
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const eth_rx_burst_t nix_eth_rx_burst[2][2][2][2][2][2][2] = {
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#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
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[f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_##name,
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NIX_RX_FASTPATH_MODES
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#undef R
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};
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const eth_rx_burst_t nix_eth_rx_burst_mseg[2][2][2][2][2][2][2] = {
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#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
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[f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_mseg_##name,
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NIX_RX_FASTPATH_MODES
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#undef R
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};
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const eth_rx_burst_t nix_eth_rx_vec_burst[2][2][2][2][2][2][2] = {
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#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
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[f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_vec_##name,
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NIX_RX_FASTPATH_MODES
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#undef R
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};
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const eth_rx_burst_t nix_eth_rx_vec_burst_mseg[2][2][2][2][2][2][2] = {
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#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
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[f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_vec_mseg_##name,
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NIX_RX_FASTPATH_MODES
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#undef R
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};
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/* Copy multi seg version with no offload for tear down sequence */
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if (rte_eal_process_type() == RTE_PROC_PRIMARY)
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dev->rx_pkt_burst_no_offload =
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nix_eth_rx_burst_mseg[0][0][0][0][0][0][0];
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if (dev->scalar_ena) {
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if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
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return pick_rx_func(eth_dev, nix_eth_rx_burst_mseg);
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return pick_rx_func(eth_dev, nix_eth_rx_burst);
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}
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if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
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return pick_rx_func(eth_dev, nix_eth_rx_vec_burst_mseg);
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return pick_rx_func(eth_dev, nix_eth_rx_vec_burst);
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}
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