27e71c7fdc
in 18.08 new cache-aligned structure rte_crypto_asym_op was introduced. As it also was included into rte_crypto_op, it caused implicit change in rte_crypto_op layout and alignment: now rte_crypto_op is cache-line aligned has a hole of 40/104 bytes between phys_addr and sym/asym op. It looks like unintended ABI breakage, plus such change can cause negative performance effects: - now status and sym[0].m_src lies on different cache-lines, so post-process code would need extra cache-line read. - new alignment causes grow of the space requirements and cache-line reads/updates for structures that contain rte_crypto_op inside. As there seems no actual need to have rte_crypto_asym_op cache-line aligned, and rte_crypto_asym_op is not intended to be used on it's own - the simplest fix is just to remove cache-line alignment for it. As the immediate positive effect: on IA ipsec-secgw performance increased by 5-10% (depending on the crypto-dev and algo used). My guess that on machines with 128B cache-line and lookaside-protocol capable crypto devices the impact will be even more noticeable. Fixes: 26008aaed14c ("cryptodev: add asymmetric xform and op definitions") Cc: stable@dpdk.org Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Fiona Trahe <fiona.trahe@intel.com> Acked-by: Shally Verma <shallyv@marvell.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
13 lines
331 B
Meson
13 lines
331 B
Meson
# SPDX-License-Identifier: BSD-3-Clause
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# Copyright(c) 2017-2019 Intel Corporation
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version = 7
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allow_experimental_apis = true
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sources = files('rte_cryptodev.c', 'rte_cryptodev_pmd.c')
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headers = files('rte_cryptodev.h',
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'rte_cryptodev_pmd.h',
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'rte_crypto.h',
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'rte_crypto_sym.h',
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'rte_crypto_asym.h')
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deps += ['kvargs', 'mbuf']
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