dc496974cd
Clarify Intel copyright and update the date to 2020.
Fixes: f3202a097f12 ("net/ice/base: add ACL module")
Fixes: a90fae1d0755 ("net/ice/base: add admin queue structures and commands")
Fixes: 2d2bdc026737 ("net/ice/base: add various headers")
Fixes: c9e37832c95f ("net/ice/base: rework on bit ops")
Fixes: 453d087ccaff ("net/ice/base: add common functions")
Fixes: 6c1f26be50a2 ("net/ice/base: add control queue information")
Fixes: 1082f786547e ("net/ice/base: support DCB")
Fixes: 6aa406714a65 ("net/ice/base: add device IDs for Intel E800 Series NICs")
Fixes: bd984f155f49 ("net/ice/base: support FDIR")
Fixes: 51d04e4933e3 ("net/ice/base: add flexible pipeline module")
Fixes: 2d2bdc026737 ("net/ice/base: add various headers")
Fixes: aa1cd410fa64 ("net/ice/base: add flow module")
Fixes: 51c7f09f3f81 ("net/ice/base: add registers for Intel E800 Series NIC")
Fixes: 64e9587d5629 ("net/ice/base: add structures for Rx/Tx queues")
Fixes: 557fa75bcf55 ("net/ice/base: add code to work with the NVM")
Fixes: b06499a43394 ("net/ice/base: update Boot Configuration Section read of NVM")
Fixes: 04b8ec1ea807 ("net/ice/base: add protocol structures and defines")
Fixes: 2a27e0a16d29 ("net/ice/base: add sideband queue info")
Fixes: 93e84b1bfc92 ("net/ice/base: add basic Tx scheduler")
Fixes: c7dd15931183 ("net/ice/base: add virtual switch code")
Fixes: a240ff50505b ("net/ice/base: add basic structures")
Cc: stable@dpdk.org
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
98 lines
3.2 KiB
C
98 lines
3.2 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2001-2020 Intel Corporation
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*/
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#ifndef _ICE_NVM_H_
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#define _ICE_NVM_H_
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#define ICE_NVM_CMD_READ 0x0000000B
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#define ICE_NVM_CMD_WRITE 0x0000000C
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/* NVM Access config bits */
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#define ICE_NVM_CFG_MODULE_M MAKEMASK(0xFF, 0)
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#define ICE_NVM_CFG_MODULE_S 0
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#define ICE_NVM_CFG_FLAGS_M MAKEMASK(0xF, 8)
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#define ICE_NVM_CFG_FLAGS_S 8
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#define ICE_NVM_CFG_EXT_FLAGS_M MAKEMASK(0xF, 12)
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#define ICE_NVM_CFG_EXT_FLAGS_S 12
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#define ICE_NVM_CFG_ADAPTER_INFO_M MAKEMASK(0xFFFF, 16)
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#define ICE_NVM_CFG_ADAPTER_INFO_S 16
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/* NVM Read Get Driver Features */
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#define ICE_NVM_GET_FEATURES_MODULE 0xE
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#define ICE_NVM_GET_FEATURES_FLAGS 0xF
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/* NVM Read/Write Mapped Space */
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#define ICE_NVM_REG_RW_MODULE 0x0
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#define ICE_NVM_REG_RW_FLAGS 0x1
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#define ICE_NVM_ACCESS_MAJOR_VER 0
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#define ICE_NVM_ACCESS_MINOR_VER 5
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/* NVM Access feature flags. Other bits in the features field are reserved and
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* should be set to zero when reporting the ice_nvm_features structure.
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*/
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#define ICE_NVM_FEATURES_0_REG_ACCESS BIT(1)
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/* NVM Access Features */
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struct ice_nvm_features {
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u8 major; /* Major version (informational only) */
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u8 minor; /* Minor version (informational only) */
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u16 size; /* size of ice_nvm_features structure */
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u8 features[12]; /* Array of feature bits */
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};
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/* NVM Access command */
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struct ice_nvm_access_cmd {
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u32 command; /* NVM command: READ or WRITE */
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u32 config; /* NVM command configuration */
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u32 offset; /* offset to read/write, in bytes */
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u32 data_size; /* size of data field, in bytes */
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};
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/* NVM Access data */
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union ice_nvm_access_data {
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u32 regval; /* Storage for register value */
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struct ice_nvm_features drv_features; /* NVM features */
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};
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/* NVM Access registers */
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#define GL_HIDA(_i) (0x00082000 + ((_i) * 4))
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#define GL_HIBA(_i) (0x00081000 + ((_i) * 4))
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#define GL_HICR 0x00082040
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#define GL_HICR_EN 0x00082044
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#define GLGEN_CSR_DEBUG_C 0x00075750
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#define GLPCI_LBARCTRL 0x0009DE74
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#define GLNVM_GENS 0x000B6100
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#define GLNVM_FLA 0x000B6108
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#define ICE_NVM_ACCESS_GL_HIDA_MAX 15
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#define ICE_NVM_ACCESS_GL_HIBA_MAX 1023
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u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd);
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u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd);
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u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd);
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enum ice_status
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ice_nvm_access_read(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
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union ice_nvm_access_data *data);
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enum ice_status
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ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
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union ice_nvm_access_data *data);
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enum ice_status
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ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,
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union ice_nvm_access_data *data);
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enum ice_status
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ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
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union ice_nvm_access_data *data);
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enum ice_status
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ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,
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bool read_shadow_ram);
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enum ice_status
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ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
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u16 module_type);
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enum ice_status ice_init_nvm(struct ice_hw *hw);
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enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data);
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enum ice_status
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ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data);
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#endif /* _ICE_NVM_H_ */
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