fd61c749db
NICs uses different delays up to a second during their configuration. It makes no sense to busy-wait so long wasting CPU cycles and preventing any other threads to execute on the same CPU core. These busy polling are the rudiments that came from the kernel drivers where you can not sleep in interrupt context, but as we're in userspace, we're able and should sleep to allow other threads to run. Delays never called on rx/tx path, so this should not affect performance. Signed-off-by: Ilya Maximets <i.maximets@samsung.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
143 lines
4.0 KiB
C
143 lines
4.0 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2001-2018
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*/
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#ifndef _IXGBE_OS_H_
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#define _IXGBE_OS_H_
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#include <string.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <rte_common.h>
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#include <rte_debug.h>
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#include <rte_cycles.h>
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#include <rte_log.h>
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#include <rte_byteorder.h>
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#include <rte_io.h>
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#include "../ixgbe_logs.h"
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#include "../ixgbe_bypass_defines.h"
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#define ASSERT(x) if(!(x)) rte_panic("IXGBE: x")
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#define DELAY(x) rte_delay_us_sleep(x)
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#define usec_delay(x) DELAY(x)
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#define msec_delay(x) DELAY(1000*(x))
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#define DEBUGFUNC(F) DEBUGOUT(F "\n");
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#define DEBUGOUT(S, args...) PMD_DRV_LOG_RAW(DEBUG, S, ##args)
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#define DEBUGOUT1(S, args...) DEBUGOUT(S, ##args)
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#define DEBUGOUT2(S, args...) DEBUGOUT(S, ##args)
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#define DEBUGOUT3(S, args...) DEBUGOUT(S, ##args)
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#define DEBUGOUT6(S, args...) DEBUGOUT(S, ##args)
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#define DEBUGOUT7(S, args...) DEBUGOUT(S, ##args)
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#define ERROR_REPORT1(e, S, args...) DEBUGOUT(S, ##args)
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#define ERROR_REPORT2(e, S, args...) DEBUGOUT(S, ##args)
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#define ERROR_REPORT3(e, S, args...) DEBUGOUT(S, ##args)
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#define FALSE 0
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#define TRUE 1
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#define false 0
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#define true 1
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#define min(a,b) RTE_MIN(a,b)
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#define EWARN(hw, S, args...) DEBUGOUT1(S, ##args)
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/* Bunch of defines for shared code bogosity */
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#define UNREFERENCED_PARAMETER(_p)
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#define UNREFERENCED_1PARAMETER(_p)
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#define UNREFERENCED_2PARAMETER(_p, _q)
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#define UNREFERENCED_3PARAMETER(_p, _q, _r)
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#define UNREFERENCED_4PARAMETER(_p, _q, _r, _s)
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#define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t)
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/* Shared code error reporting */
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enum {
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IXGBE_ERROR_SOFTWARE,
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IXGBE_ERROR_POLLING,
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IXGBE_ERROR_INVALID_STATE,
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IXGBE_ERROR_UNSUPPORTED,
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IXGBE_ERROR_ARGUMENT,
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IXGBE_ERROR_CAUTION,
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};
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#define STATIC static
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#define IXGBE_NTOHL(_i) rte_be_to_cpu_32(_i)
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#define IXGBE_NTOHS(_i) rte_be_to_cpu_16(_i)
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#define IXGBE_CPU_TO_LE16(_i) rte_cpu_to_le_16(_i)
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#define IXGBE_CPU_TO_LE32(_i) rte_cpu_to_le_32(_i)
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#define IXGBE_LE32_TO_CPU(_i) rte_le_to_cpu_32(_i)
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#define IXGBE_LE32_TO_CPUS(_i) rte_le_to_cpu_32(_i)
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#define IXGBE_CPU_TO_BE16(_i) rte_cpu_to_be_16(_i)
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#define IXGBE_CPU_TO_BE32(_i) rte_cpu_to_be_32(_i)
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#define IXGBE_BE32_TO_CPU(_i) rte_be_to_cpu_32(_i)
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typedef uint8_t u8;
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typedef int8_t s8;
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typedef uint16_t u16;
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typedef int16_t s16;
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typedef uint32_t u32;
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typedef int32_t s32;
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typedef uint64_t u64;
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#ifndef __cplusplus
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typedef int bool;
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#endif
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#define mb() rte_mb()
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#define wmb() rte_wmb()
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#define rmb() rte_rmb()
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#define IOMEM
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#define prefetch(x) rte_prefetch0(x)
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#define IXGBE_PCI_REG(reg) rte_read32(reg)
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static inline uint32_t ixgbe_read_addr(volatile void* addr)
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{
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return rte_le_to_cpu_32(IXGBE_PCI_REG(addr));
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}
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#define IXGBE_PCI_REG_WRITE(reg, value) \
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rte_write32((rte_cpu_to_le_32(value)), reg)
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#define IXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
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rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
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#define IXGBE_PCI_REG_ADDR(hw, reg) \
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((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
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#define IXGBE_PCI_REG_ARRAY_ADDR(hw, reg, index) \
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IXGBE_PCI_REG_ADDR((hw), (reg) + ((index) << 2))
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/* Not implemented !! */
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#define IXGBE_READ_PCIE_WORD(hw, reg) 0
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#define IXGBE_WRITE_PCIE_WORD(hw, reg, value) do { } while(0)
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#define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
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#define IXGBE_READ_REG(hw, reg) \
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ixgbe_read_addr(IXGBE_PCI_REG_ADDR((hw), (reg)))
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#define IXGBE_WRITE_REG(hw, reg, value) \
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IXGBE_PCI_REG_WRITE(IXGBE_PCI_REG_ADDR((hw), (reg)), (value))
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#define IXGBE_READ_REG_ARRAY(hw, reg, index) \
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IXGBE_PCI_REG(IXGBE_PCI_REG_ARRAY_ADDR((hw), (reg), (index)))
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#define IXGBE_WRITE_REG_ARRAY(hw, reg, index, value) \
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IXGBE_PCI_REG_WRITE(IXGBE_PCI_REG_ARRAY_ADDR((hw), (reg), (index)), (value))
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#define IXGBE_WRITE_REG_THEN_POLL_MASK(hw, reg, val, mask, poll_ms) \
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do { \
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uint32_t cnt = poll_ms; \
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IXGBE_WRITE_REG(hw, (reg), (val)); \
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while (((IXGBE_READ_REG(hw, (reg))) & (mask)) && (cnt--)) \
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rte_delay_ms(1); \
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} while (0)
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#endif /* _IXGBE_OS_H_ */
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