fc1f2750a3
The 1.7 DPDK_Prog_Guide document in MSWord has been converted to rst format for use with Sphinx. There is an rst file for each chapter and an index.rst file which contains the table of contents. The top level index file has been modified to include this guide. This document contains some png image files. If any of these png files are modified they should be replaced with an svg file. This is the sixth document from a set of 6 documents. Signed-off-by: Bernard Iremonger <bernard.iremonger@intel.com>
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.. BSD LICENSE
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Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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Programmer's Guide
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==================
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June 2014
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
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TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS,
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INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY
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OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
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A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death.
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SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES,
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AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY,
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ANY CLAIM OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION,
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WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS.
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Intel may make changes to specifications and product descriptions at any time, without notice.
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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined".
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Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
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The information here is subject to change without notice. Do not finalize a design with this information.
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The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
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Current characterized errata are available on request.
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Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548- 4725,
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or go to: http://www.intel.com/design/literature.htm.
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Any software source code reprinted in this document is furnished for informational purposes only and may only be used or copied and no license, express or implied,
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by estoppel or otherwise, to any of the reprinted source code is granted by this document.
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Code Names are only for use by Intel to identify products, platforms, programs, services, etc.
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("products") in development by Intel that have not been made commercially available to the public, i.e., announced, launched or shipped.
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They are never to be used as "commercial" names for products. Also, they are not intended to function as trademarks.
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Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries.
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\*Other names and brands may be claimed as the property of others.
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Copyright © 2012-2014, Intel Corporation. All rights reserved.
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**Contents**
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.. toctree::
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:maxdepth: 3
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:numbered:
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intro
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overview
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env_abstraction_layer
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malloc_lib
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ring_lib
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mempool_lib
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mbuf_lib
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poll_mode_drv
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i40e_ixgbe_igb_virt_func_drv
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driver_vm_emul_dev
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ivshmem_lib
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poll_mode_drv_emulated_virtio_nic
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poll_mode_drv_paravirtual_vmxnets_nic
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intel_dpdk_xen_based_packet_switch_sol
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libpcap_ring_based_poll_mode_drv
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link_bonding_poll_mode_drv_lib
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timer_lib
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hash_lib
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lpm_lib
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lpm6_lib
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packet_distrib_lib
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ip_fragment_reassembly_lib
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multi_proc_support
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kernel_nic_interface
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thread_safety_intel_dpdk_functions
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qos_framework
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power_man
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packet_classif_access_ctrl
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packet_framework
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source_org
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dev_kit_build_system
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dev_kit_root_make_help
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extend_intel_dpdk
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build_app
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ext_app_lib_make_help
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perf_opt_guidelines
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writing_efficient_code
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profile_app
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glossary
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**Figures**
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:ref:`Figure 1. Core Components Architecture <pg_figure_1>`
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:ref:`Figure 2. EAL Initialization in a Linux Application Environment <pg_figure_2>`
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:ref:`Figure 3. Example of a malloc heap and malloc elements within the malloc library <pg_figure_3>`
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:ref:`Figure 4. Ring Structure <pg_figure_4>`
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:ref:`Figure 5. Two Channels and Quad-ranked DIMM Example <pg_figure_5>`
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:ref:`Figure 6. Three Channels and Two Dual-ranked DIMM Example <pg_figure_6>`
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:ref:`Figure 7. A mempool in Memory with its Associated Ring <pg_figure_7>`
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:ref:`Figure 8. An mbuf with One Segment <pg_figure_8>`
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:ref:`Figure 9. An mbuf with Three Segments <pg_figure_9>`
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:ref:`Figure 10. Virtualization for a Single Port NIC in SR-IOV Mode <pg_figure_10>`
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:ref:`Figure 11. Performance Benchmark Setup <pg_figure_11>`
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:ref:`Figure 12. Fast Host-based Packet Processing <pg_figure_12>`
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:ref:`Figure 13. Inter-VM Communication <pg_figure_13>`
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:ref:`Figure 14. Host2VM Communication Example Using kni vhost Back End <pg_figure_14>`
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:ref:`Figure 15. Host2VM Communication Example Using qemu vhost Back End <pg_figure_15>`
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:ref:`Figure 16. Memory Sharing inthe Intel® DPDK Multi-process Sample Application <pg_figure_16>`
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:ref:`Figure 17. Components of an Intel® DPDK KNI Application <pg_figure_17>`
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:ref:`Figure 18. Packet Flow via mbufs in the Intel DPDK® KNI <pg_figure_18>`
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:ref:`Figure 19. vHost-net Architecture Overview <pg_figure_19>`
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:ref:`Figure 20. KNI Traffic Flow <pg_figure_20>`
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:ref:`Figure 21. Complex Packet Processing Pipeline with QoS Support <pg_figure_21>`
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:ref:`Figure 22. Hierarchical Scheduler Block Internal Diagram <pg_figure_22>`
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:ref:`Figure 23. Scheduling Hierarchy per Port <pg_figure_23>`
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:ref:`Figure 24. Internal Data Structures per Port <pg_figure_24>`
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:ref:`Figure 25. Prefetch Pipeline for the Hierarchical Scheduler Enqueue Operation <pg_figure_25>`
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:ref:`Figure 26. Pipe Prefetch State Machine for the Hierarchical Scheduler Dequeue Operation <pg_figure_26>`
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:ref:`Figure 27. High-level Block Diagram of the Intel® DPDK Dropper <pg_figure_27>`
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:ref:`Figure 28. Flow Through the Dropper <pg_figure_28>`
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:ref:`Figure 29. Example Data Flow Through Dropper <pg_figure_29>`
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:ref:`Figure 30. Packet Drop Probability for a Given RED Configuration <pg_figure_30>`
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:ref:`Figure 31. Initial Drop Probability (pb), Actual Drop probability (pa) Computed Using a Factor 1 (Blue Curve) and a Factor 2 (Red Curve) <pg_figure_31>`
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:ref:`Figure 32. Example of packet processing pipeline. The input ports 0 and 1 are connected with the output ports 0, 1 and 2 through tables 0 and 1. <pg_figure_32>`
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:ref:`Figure 33. Sequence of steps for hash table operations in packet processing context <pg_figure_33>`
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:ref:`Figure 34. Data structures for configurable key size hash tables <pg_figure_34>`
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:ref:`Figure 35. Bucket search pipeline for key lookup operation (configurable key size hash tables) <pg_figure_35>`
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:ref:`Figure 36. Pseudo-code for match, match_many and match_pos <pg_figure_36>`
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:ref:`Figure 37. Data structures for 8-byte key hash tables <pg_figure_37>`
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:ref:`Figure 38. Data structures for 16-byte key hash tables <pg_figure_38>`
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:ref:`Figure 39. Bucket search pipeline for key lookup operation (single key size hash tables) <pg_figure_39>`
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**Tables**
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:ref:`Table 1. Packet Processing Pipeline Implementing QoS <pg_table_1>`
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:ref:`Table 2. Infrastructure Blocks Used by the Packet Processing Pipeline <pg_table_2>`
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:ref:`Table 3. Port Scheduling Hierarchy <pg_table_3>`
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:ref:`Table 4. Scheduler Internal Data Structures per Port <pg_table_4>`
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:ref:`Table 5. Ethernet Frame Overhead Fields <pg_table_5>`
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:ref:`Table 6. Token Bucket Generic Operations <pg_table_6>`
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:ref:`Table 7. Token Bucket Generic Parameters <pg_table_7>`
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:ref:`Table 8. Token Bucket Persistent Data Structure <pg_table_8>`
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:ref:`Table 9. Token Bucket Operations <pg_table_9>`
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:ref:`Table 10. Subport/Pipe Traffic Class Upper Limit Enforcement Persistent Data Structure <pg_table_10>`
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:ref:`Table 11. Subport/Pipe Traffic Class Upper Limit Enforcement Operations <pg_table_11>`
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:ref:`Table 12. Weighted Round Robin (WRR) <pg_table_12>`
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:ref:`Table 13. Subport Traffic Class Oversubscription <pg_table_13>`
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:ref:`Table 14. Watermark Propagation from Subport Level to Member Pipes at the Beginning of Each Traffic Class Upper Limit Enforcement Period <pg_table_14>`
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:ref:`Table 15. Watermark Calculation <pg_table_15>`
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:ref:`Table 16. RED Configuration Parameters <pg_table_16>`
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:ref:`Table 17. Relative Performance of Alternative Approaches <pg_table_17>`
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:ref:`Table 18. RED Configuration Corresponding to RED Configuration File <pg_table_18>`
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:ref:`Table 19. Port types <pg_table_19>`
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:ref:`Table 20. Port abstract interface <pg_table_20>`
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:ref:`Table 21. Table types <pg_table_21>`
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:ref:`Table 29. Table Abstract Interface <pg_table_29_1>`
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:ref:`Table 22. Configuration parameters common for all hash table types <pg_table_22>`
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:ref:`Table 23. Configuration parameters specific to extendible bucket hash table <pg_table_23>`
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:ref:`Table 24. Configuration parameters specific to pre-computed key signature hash table <pg_table_24>`
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:ref:`Table 25. The main large data structures (arrays) used for configurable key size hash tables <pg_table_25>`
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:ref:`Table 26. Field description for bucket array entry (configurable key size hash tables) <pg_table_26>`
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:ref:`Table 27. Description of the bucket search pipeline stages (configurable key size hash tables) <pg_table_27>`
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:ref:`Table 28. Lookup tables for match, match_many, match_pos <pg_table_28>`
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:ref:`Table 29. Collapsed lookup tables for match, match_many and match_pos <pg_table_29>`
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:ref:`Table 30. The main large data structures (arrays) used for 8-byte and 16-byte key size hash tables <pg_table_30>`
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:ref:`Table 31. Field description for bucket array entry (8-byte and 16-byte key hash tables) <pg_table_31>`
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:ref:`Table 32. Description of the bucket search pipeline stages (8-byte and 16-byte key hash tables) <pg_table_32>`
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:ref:`Table 33. Next hop actions (reserved) <pg_table_33>`
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:ref:`Table 34. User action examples <pg_table_34>`
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