4ac7516b8b
Added device phy initialization, read/write and other maintenance apis to be used within PMD. Signed-off-by: Ravi Kumar <ravi1.kumar@amd.com>
332 lines
7.6 KiB
C
332 lines
7.6 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
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* Copyright(c) 2018 Synopsys, Inc. All rights reserved.
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*/
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#include "axgbe_ethdev.h"
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#include "axgbe_common.h"
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#define AXGBE_ABORT_COUNT 500
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#define AXGBE_DISABLE_COUNT 1000
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#define AXGBE_STD_SPEED 1
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#define AXGBE_INTR_RX_FULL BIT(IC_RAW_INTR_STAT_RX_FULL_INDEX)
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#define AXGBE_INTR_TX_EMPTY BIT(IC_RAW_INTR_STAT_TX_EMPTY_INDEX)
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#define AXGBE_INTR_TX_ABRT BIT(IC_RAW_INTR_STAT_TX_ABRT_INDEX)
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#define AXGBE_INTR_STOP_DET BIT(IC_RAW_INTR_STAT_STOP_DET_INDEX)
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#define AXGBE_DEFAULT_INT_MASK (AXGBE_INTR_RX_FULL | \
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AXGBE_INTR_TX_EMPTY | \
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AXGBE_INTR_TX_ABRT | \
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AXGBE_INTR_STOP_DET)
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#define AXGBE_I2C_READ BIT(8)
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#define AXGBE_I2C_STOP BIT(9)
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static int axgbe_i2c_abort(struct axgbe_port *pdata)
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{
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unsigned int wait = AXGBE_ABORT_COUNT;
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/* Must be enabled to recognize the abort request */
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XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, 1);
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/* Issue the abort */
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XI2C_IOWRITE_BITS(pdata, IC_ENABLE, ABORT, 1);
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while (wait--) {
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if (!XI2C_IOREAD_BITS(pdata, IC_ENABLE, ABORT))
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return 0;
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rte_delay_us(500);
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}
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return -EBUSY;
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}
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static int axgbe_i2c_set_enable(struct axgbe_port *pdata, bool enable)
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{
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unsigned int wait = AXGBE_DISABLE_COUNT;
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unsigned int mode = enable ? 1 : 0;
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while (wait--) {
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XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, mode);
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if (XI2C_IOREAD_BITS(pdata, IC_ENABLE_STATUS, EN) == mode)
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return 0;
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rte_delay_us(100);
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}
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return -EBUSY;
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}
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static int axgbe_i2c_disable(struct axgbe_port *pdata)
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{
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unsigned int ret;
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ret = axgbe_i2c_set_enable(pdata, false);
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if (ret) {
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/* Disable failed, try an abort */
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ret = axgbe_i2c_abort(pdata);
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if (ret)
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return ret;
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/* Abort succeeded, try to disable again */
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ret = axgbe_i2c_set_enable(pdata, false);
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}
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return ret;
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}
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static int axgbe_i2c_enable(struct axgbe_port *pdata)
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{
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return axgbe_i2c_set_enable(pdata, true);
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}
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static void axgbe_i2c_clear_all_interrupts(struct axgbe_port *pdata)
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{
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XI2C_IOREAD(pdata, IC_CLR_INTR);
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}
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static void axgbe_i2c_disable_interrupts(struct axgbe_port *pdata)
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{
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XI2C_IOWRITE(pdata, IC_INTR_MASK, 0);
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}
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static void axgbe_i2c_enable_interrupts(struct axgbe_port *pdata)
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{
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XI2C_IOWRITE(pdata, IC_INTR_MASK, AXGBE_DEFAULT_INT_MASK);
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}
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static void axgbe_i2c_write(struct axgbe_port *pdata)
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{
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struct axgbe_i2c_op_state *state = &pdata->i2c.op_state;
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unsigned int tx_slots;
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unsigned int cmd;
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/* Configured to never receive Rx overflows, so fill up Tx fifo */
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tx_slots = pdata->i2c.tx_fifo_size - XI2C_IOREAD(pdata, IC_TXFLR);
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while (tx_slots && state->tx_len) {
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if (state->op->cmd == AXGBE_I2C_CMD_READ)
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cmd = AXGBE_I2C_READ;
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else
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cmd = *state->tx_buf++;
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if (state->tx_len == 1)
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XI2C_SET_BITS(cmd, IC_DATA_CMD, STOP, 1);
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XI2C_IOWRITE(pdata, IC_DATA_CMD, cmd);
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tx_slots--;
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state->tx_len--;
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}
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/* No more Tx operations, so ignore TX_EMPTY and return */
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if (!state->tx_len)
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XI2C_IOWRITE_BITS(pdata, IC_INTR_MASK, TX_EMPTY, 0);
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}
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static void axgbe_i2c_read(struct axgbe_port *pdata)
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{
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struct axgbe_i2c_op_state *state = &pdata->i2c.op_state;
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unsigned int rx_slots;
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/* Anything to be read? */
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if (state->op->cmd != AXGBE_I2C_CMD_READ)
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return;
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rx_slots = XI2C_IOREAD(pdata, IC_RXFLR);
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while (rx_slots && state->rx_len) {
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*state->rx_buf++ = XI2C_IOREAD(pdata, IC_DATA_CMD);
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state->rx_len--;
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rx_slots--;
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}
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}
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static void axgbe_i2c_clear_isr_interrupts(struct axgbe_port *pdata,
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unsigned int isr)
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{
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struct axgbe_i2c_op_state *state = &pdata->i2c.op_state;
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if (isr & AXGBE_INTR_TX_ABRT) {
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state->tx_abort_source = XI2C_IOREAD(pdata, IC_TX_ABRT_SOURCE);
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XI2C_IOREAD(pdata, IC_CLR_TX_ABRT);
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}
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if (isr & AXGBE_INTR_STOP_DET)
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XI2C_IOREAD(pdata, IC_CLR_STOP_DET);
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}
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static int axgbe_i2c_isr(struct axgbe_port *pdata)
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{
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struct axgbe_i2c_op_state *state = &pdata->i2c.op_state;
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unsigned int isr;
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isr = XI2C_IOREAD(pdata, IC_RAW_INTR_STAT);
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axgbe_i2c_clear_isr_interrupts(pdata, isr);
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if (isr & AXGBE_INTR_TX_ABRT) {
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axgbe_i2c_disable_interrupts(pdata);
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state->ret = -EIO;
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goto out;
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}
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/* Check for data in the Rx fifo */
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axgbe_i2c_read(pdata);
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/* Fill up the Tx fifo next */
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axgbe_i2c_write(pdata);
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out:
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/* Complete on an error or STOP condition */
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if (state->ret || XI2C_GET_BITS(isr, IC_RAW_INTR_STAT, STOP_DET))
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return 1;
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return 0;
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}
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static void axgbe_i2c_set_mode(struct axgbe_port *pdata)
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{
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unsigned int reg;
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reg = XI2C_IOREAD(pdata, IC_CON);
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XI2C_SET_BITS(reg, IC_CON, MASTER_MODE, 1);
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XI2C_SET_BITS(reg, IC_CON, SLAVE_DISABLE, 1);
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XI2C_SET_BITS(reg, IC_CON, RESTART_EN, 1);
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XI2C_SET_BITS(reg, IC_CON, SPEED, AXGBE_STD_SPEED);
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XI2C_SET_BITS(reg, IC_CON, RX_FIFO_FULL_HOLD, 1);
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XI2C_IOWRITE(pdata, IC_CON, reg);
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}
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static void axgbe_i2c_get_features(struct axgbe_port *pdata)
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{
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struct axgbe_i2c *i2c = &pdata->i2c;
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unsigned int reg;
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reg = XI2C_IOREAD(pdata, IC_COMP_PARAM_1);
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i2c->max_speed_mode = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
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MAX_SPEED_MODE);
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i2c->rx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
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RX_BUFFER_DEPTH);
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i2c->tx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
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TX_BUFFER_DEPTH);
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}
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static void axgbe_i2c_set_target(struct axgbe_port *pdata, unsigned int addr)
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{
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XI2C_IOWRITE(pdata, IC_TAR, addr);
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}
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static int axgbe_i2c_xfer(struct axgbe_port *pdata, struct axgbe_i2c_op *op)
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{
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struct axgbe_i2c_op_state *state = &pdata->i2c.op_state;
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int ret;
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uint64_t timeout;
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pthread_mutex_lock(&pdata->i2c_mutex);
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ret = axgbe_i2c_disable(pdata);
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if (ret) {
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PMD_DRV_LOG(ERR, "failed to disable i2c master\n");
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return ret;
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}
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axgbe_i2c_set_target(pdata, op->target);
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memset(state, 0, sizeof(*state));
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state->op = op;
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state->tx_len = op->len;
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state->tx_buf = (unsigned char *)op->buf;
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state->rx_len = op->len;
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state->rx_buf = (unsigned char *)op->buf;
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axgbe_i2c_clear_all_interrupts(pdata);
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ret = axgbe_i2c_enable(pdata);
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if (ret) {
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PMD_DRV_LOG(ERR, "failed to enable i2c master\n");
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return ret;
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}
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/* Enabling the interrupts will cause the TX FIFO empty interrupt to
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* fire and begin to process the command via the ISR.
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*/
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axgbe_i2c_enable_interrupts(pdata);
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timeout = rte_get_timer_cycles() + rte_get_timer_hz();
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while (time_before(rte_get_timer_cycles(), timeout)) {
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rte_delay_us(100);
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if (XI2C_IOREAD(pdata, IC_RAW_INTR_STAT)) {
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if (axgbe_i2c_isr(pdata))
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goto success;
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}
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}
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PMD_DRV_LOG(ERR, "i2c operation timed out\n");
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axgbe_i2c_disable_interrupts(pdata);
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axgbe_i2c_disable(pdata);
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ret = -ETIMEDOUT;
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goto unlock;
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success:
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ret = state->ret;
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if (ret) {
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if (state->tx_abort_source & IC_TX_ABRT_7B_ADDR_NOACK)
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ret = -ENOTCONN;
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else if (state->tx_abort_source & IC_TX_ABRT_ARB_LOST)
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ret = -EAGAIN;
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}
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unlock:
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pthread_mutex_unlock(&pdata->i2c_mutex);
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return ret;
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}
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static void axgbe_i2c_stop(struct axgbe_port *pdata)
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{
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if (!pdata->i2c.started)
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return;
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pdata->i2c.started = 0;
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axgbe_i2c_disable_interrupts(pdata);
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axgbe_i2c_disable(pdata);
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axgbe_i2c_clear_all_interrupts(pdata);
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}
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static int axgbe_i2c_start(struct axgbe_port *pdata)
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{
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if (pdata->i2c.started)
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return 0;
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pdata->i2c.started = 1;
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return 0;
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}
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static int axgbe_i2c_init(struct axgbe_port *pdata)
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{
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int ret;
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axgbe_i2c_disable_interrupts(pdata);
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ret = axgbe_i2c_disable(pdata);
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if (ret) {
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PMD_DRV_LOG(ERR, "failed to disable i2c master\n");
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return ret;
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}
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axgbe_i2c_get_features(pdata);
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axgbe_i2c_set_mode(pdata);
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axgbe_i2c_clear_all_interrupts(pdata);
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return 0;
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}
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void axgbe_init_function_ptrs_i2c(struct axgbe_i2c_if *i2c_if)
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{
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i2c_if->i2c_init = axgbe_i2c_init;
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i2c_if->i2c_start = axgbe_i2c_start;
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i2c_if->i2c_stop = axgbe_i2c_stop;
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i2c_if->i2c_xfer = axgbe_i2c_xfer;
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}
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